United Microelectronics Corp.

Other

Kun-Lin Wu

Horng-Bor Lu

Chien-Hsin Lai

Peng-Yih Peng

Juen-Kuen Lin

Hao-Kuang Chiu

Meng-Jin Tsai

Juan-Yuan Wu

Chih-Chiang Yang

Daniel Chiu

Jenn-Tarng Lin

Fu-Yang Yu

Yu-Tsai Lin

Shyan-Yhu Wang

Cheng-Jung Hsu

Jacques Rajotte

Edward Yang

Hao-Kuang Shiu

Chien-Hsien Lai

J J Huang

Jyh-J Huang

Chi-Jung Lin

A screw driving device for an impact driver has cylindrical clutch bearings with frustoconical inner ends that contact a screw bit retained by the screw driving device to drive a screw to a predetermined depth in a workpiece and release the screw bit in a clutched position that is achieved when the screw has been driven to the predetermined depth in the workpiece.

Screw driving device for use with an impact driver

A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Chemical mechanical polishing method

A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Chemical-mechanical polishing method

A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 &#x212b; can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiHCl) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.

Method for forming improved high resistance resistor by treating the surface of polysilicon layer

The present invention provides a method of preventing the dishing phenomenon occurring atop a dual damascene structure on a semiconductor wafer. The semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and both the surface of the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure to remove portions of the barrier layer uncovered by the photoresist layer. Finally, a second CMP process is performed to remove portions of the copper layer so as to align the top of the copper layer in the dual damascene structure with the surface of the first dielectric layer after the photoresist layer is stripped.

Method of preventing dishing phenomenon atop a dual damascene structure

A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.

Method for preventing aluminum intrusions

A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

Chemical-mechanical polish machines and fabrication process using the same

Chemical mechanical polish machines and fabrication process using the same

A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an implantation process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Method for preventing poisoned vias and trenches

A method for forming capacitor is proposed. The key point of the invention is that bottom plate and dielectric layer of capacitor are formed before metal interconnect is formed. Thus, thermal treatment of dielectric layer does not affect metal interconnect. Therefore, conventional fault that quality of dielectric layer is degraded by scant annealing is avoided, and then dielectric layer and metal interconnect can be optimized respectively. Obviously, the ultimate advantage of the proposed method is that not only breakdown voltage of dielectric layer is increased by annealing but also quality of metal interconnect is not affected by annealing. Therefore, an incidental advantage of the proposed method is that the method is beneficial to form both capacitor and metal interconnect.

Method for forming capacitor

A method of fabricating shallow trench isolation. A silicon oxide layer is formed on a substrate. The silicon oxide layer is patterned and a portion of the substrate is removed to form a trench within the substrate. A liner oxide layer is formed on the sidewall of the trench. An insulating layer is formed on the substrate and filled in the trench. A portion of the insulating layer is removed by CMP to expose the silicon oxide layer. The silicon oxide layer is removed and the STI structure is completed.

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Taichung, Taiwan

Kun-Lin Wu