United Microelectronics Corp.

Kun-Huang Yu

Shih-Yin Hsiao

Shu-Wen Lin

Chih-Chung Wang

Wen-Fang Lee

Chiu-Te Lee

Ke-Feng Lin

Te-Yuan Wu

Kuan-Chuan Chen

Kai-Kuen Chang

Chin-Fu Chen

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

Memory device

A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

Method of forming semiconductor structure

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Semiconductor device and method of forming the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Semiconductor structure having a dummy contact and manufacturing method thereof

The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

High-voltage metal-oxide semiconductor transistor

A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

Metal-oxide-semiconductor transistor device and manufacturing method thereof

A high voltage metal-oxide-semiconductor transistor device having stepped gate structure and a manufacturing method thereof are provided. The manufacturing method includes following steps. A gate structure is formed on a semiconductor substrate. The semiconductor substrate includes a first region and a second region disposed on a side of a first part of the gate structure and a side of a second part of the gate structure respectively. A patterned mask layer is formed on the semiconductor substrate and the gate structure. The patterned mask layer covers the first region and the first part. The second part is uncovered by the patterned mask layer. An implantation process is performed to form a drift region in the second region. An etching process is performed to remove a part of the second part uncovered by the patterned mask layer. A thickness of the second part is less than that of the first part after the etching process.

High voltage metal-oxide-semiconductor transistor device having stepped gate structure and manufacturing method thereof

A MOS transistor device includes a substrate including a gate formed thereon, and a spacer being formed on a sidewall of the gate; a source region and a drain region formed in the substrate; and at least a first dummy contact formed above the substrate on a drain side of the gate. More important, the first dummy contact is formed apart from a surface of the substrate.

Metal-oxide-semiconductor transistor device having a drain side dummy contact

A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation. The bottom surface of the second portion of the conductive plug is covered by the isolation.

Semiconductor structure and method for manufacturing the same

High-voltage metal-oxide semiconductor transistor and method of fabricating the same

A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well and a second well respectively having the first and second conductive types formed in the deep well, and extending down from the surface of the substrate; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion comprising at least two fingers penetrating into the isolation, and the fingers spaced apart and electrically connected to each other.

A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug including a first portion and a second portion electrically connected to each other, and the first portion electrically connected to the gate electrode, and the second portion penetrating into the isolation.

A MOS transistor is described, including: a source region and a drain region in a semiconductor substrate, an isolation between the source region and the drain region, a first gate conductor between the source region and the isolation, at least one conductive plug electrically connected to the first gate conductor and penetrating into the isolation, and at least one second gate conductor on the isolation, which is electrically connected to the first gate conductor and the at least one conductive plug. One of the at least one conductive plug is between the first gate conductor and the at least one second gate conductor.

MOS transistor

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure. The dielectric layer is on an upper substrate surface of the semiconductor substrate. The dielectric structure and the semiconductor substrate have opposing first and second interfaces therebetween. The electrode structure comprises an electrode truck portion and at least one electrode branch portion. The at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure. The at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 &#x212b; therebetween.

Growing community of inventors

Taipei, Taiwan

Kun-Huang Yu