Intel Corporation

Kun-Huan Shih

Walid M Hafez

Jui-Yen Lin

Nidhi Nidhi

Curtis Tsai

Kinyip Phoa

Yi Wei Chen

Xiaodong Yang

Joodong Park

Chen-Guan Lee

An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.

Asymmetric spacer for low capacitance applications

A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

Vertical transistor using a through silicon via gate

Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

On-chip through-body-via capacitors and techniques for forming same

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Portland, OR, United States of America

Kun-Huan Shih