Samsung Electronics Co., Ltd.

Kun-Dae Yeom

Yong-kwan Lee

Keun-ho Jang

Baek Ki

Tark-Hyun Ko

Young-lyong Kim

Chul-Yong Jang

Jong-Gi Lee

Young-Shin Choi

Hyun-Jong Woo

A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.

Package substrate for a semiconductor package having landing pads extending toward a through-hole in a chip mounting region

Semiconductor package including landing pads extending at an oblique angle toward a through-hole in the package substrate

Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Printed circuit board having reliable bump interconnection structure, method of fabricating the same, and semiconductor package using the same

A unit semiconductor chip and stacked semiconductor package and method of manufacturing with center bonding pads and at least one circuit layer to reduce the length of bonding. The unit semiconductor chip includes a first series of bonding wires connected to a plurality of center bonding pads of a semiconductor chip, at least one circuit layer connected to the first series of bonding wires and including a series of circuit layer wiring patterns, and a second series of bonding wires connecting the series of circuit layer wiring patterns and a series of wiring patterns. The stacked semiconductor package further includes a second series of wiring patterns, connected to the first series of wiring patterns, the a second series of wiring patterns and the series of circuit layer wiring patterns providing connections to adjacent lower and upper unit semiconductor packages, respectively.

Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same

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Asan-si, South Korea

Kun-Dae Yeom