United Microelectronics Corp.

Kun-Chi Lin

Tzung-Han Lee

Horng-Nan Chern

King-Lung Wu

Kevin Lin

Wayne Tan

Alex Hou

Kuo-Chi Lin

Chia-Wen Liang

Gwo-Shii Yang

Ching-Chiao Hao

Kuo-Tai Huang

Benjamin Szu-Min Lin

Hal Lee

Tsu-An Lin

Chien-hua Tsai

Chien-Hua Tsai

Kuen-Yow Lin

Jin-sheng Yang

Da-Wen Shia

Hsi-Chia Lin

Horng-Non Chern

A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dished area to form an opening exposing the insulating layer; deepening the opening to expose the first conductive device; and filling the opening with a conductive material.

Method of fabricating node contacts

A multi-chip package which has a L-shaped plate and a plurality of dies arranged on the L-shaped plate. The L-shaped plate has a die package region, a plurality of solder bump pads disposed in the die package region, a plurality of pins electrically connected to a printed circuit board (PCB), and an internal circuit inside the L-shaped plate electrically connected to the plurality of solder bump pads and corresponding pins. Each die includes a plurality of bonding pads on an active surface of the die, and the bonding pads are electrically connected to corresponding solder bump pads.

Multi-die package

The present invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a plurality of gate structures above the active regions and a plurality of source/drain regions, while each gate structure comprises a top cap layer and sidewall spacers; forming a conductive layer over the substrate; removing a portion of the conductive layer above the gate structure using the top cap layer of the gate structure as a stop layer, so that a height of the conductive layer is lower than a height of the gate structure; forming a patterned mask layer, right above the active regions, over the substrate; performing an etching step to define the conductive layer above the active regions; and removing the patterned mask layer and forming landing pads on the active regions.

Method for forming landing pad

A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Method for fabricating an ultra small opening

An isolation layer is formed on a substrate of a semiconductor wafer. At least one recess is formed in the isolation layer by way of a photo-etching-process. A two stage in-situ doped deposition process is then performed to form a first doped amorphous silicon (&agr;-Si) layer and a second doped amorphous silicon (&agr;-Si) layer doping concentration of the second doped amorphous silicon (&agr;-Si) layer being less than that of the first doped amorphous silicon layer. A dielectric layer is formed to fill the recess, and a planarization process removes portions of the second doped amorphous silicon layer, the first doped amorphous silicon layer and the dielectric layer on the surface of the isolation layer. Finally, the dielectric layer and the isolation layer are removed, and a hemi-spherical grain (HSG) process is performed to form a rough surface with a plurality of hemi-spherical grains on the surface of the second doped amorphous silicon layer.

Method of forming a lower storage node of a capacitor

The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

Method of reducing stress between a nitride silicon spacer and a substrate

A method of fabricating a bottom electrode is described. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer. An isolation spacer remaining from the conformal isolation layer is formed on a sidewall of the contact node opening. A conformal conductive layer is formed in the opening and the node contact opening to make contact with the conductive plug. The third dielectric layer is removed.

Method of fabricating a bottom electrode

A method for forming an inner-cylindrical capacitor without top electrode mask is disclosed. The method includes a step of a trench formed on the substrate. The trench structure with a conductive layer as a first lower electrode. The first poly spacer as second lower electrode of inner-cylindrical capacitor formed on sidewall of the trench, and furthermore a dielectric layer is formed by depositing on sidewall of first poly spacer and a floor of the cylindrical trench. Then, the second poly spacer formed on sidewall of dielectric layer. The poly plug is formed by depositing polysilicon layer and polished by chemical mechanical polishing (CMP) process. Thus, an inner-cylindrical capacitor is generated.

Method for forming inner-cylindrical capacitor without top electrode mask

A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate. Finally, conductive material is deposited into the node contact openings and the cylindrical openings to become the lower electrodes and the node contacts respectively.

Cylindrical capacitor structure and method of manufacture

A method of manufacturing a dynamic random access memory cell. A substrate having a transistor therein is provided. A first dielectric layer is formed over the substrate and the transistor. A bit line having a cap layer thereon is formed over the first dielectric layer. A protective layer is formed over the substrate covering the bit line. A second dielectric layer is formed over the protective layer. The second dielectric layer is etched in a self-aligned process. The etching continues penetrating the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and an opening for forming the lower electrode of a capacitor are formed at the same time. Thereafter, polysilicon material is deposited into the node contact opening and the lower electrode opening to form a polysilicon layer. The upper surface of the polysilicon layer is slightly below the lower electrode opening. A spacer is formed on the sidewalls of the lower electrode opening above the polysilicon layer. Using the spacers as a mask, the polysilicon layer is etched to form a lower electrode with a recess groove above the node contact opening. The second dielectric layer and the spacers are removed. To complete the fabrication of the DRAM cell capacitor, a dielectric layer is formed over the lower electrode and an upper electrode is formed over the dielectric layer.

Method of manufacturing dynamic random access memory cell

A method for forming a cell passes transistor in DRAM process disclosed. In one embodiment, the present invention provides a MOS structure, which can reduce junction leakage for P/N junction and increase the refreshes time capability. A method for DRAM fabrication comprises providing a semiconductor substrate having at least an isolation device therein. The isolation device defines an active area adjacent thereto on the semiconductor substrate. A first photoresist layer is formed on the semiconductor substrate, which exposes the active area in a first direction. The first conductive ions are implanted to form a well region in the semiconductor substrate, and the second conductive ions are implanted to form a field implant region in the semiconductor substrate. The third conductive ions are implanted to form a punchthrough implant region in the semiconductor substrate. Then the first photoresist layer is removed, and a second photoresist layer is formed on the semiconductor substrate. The second photoresist layer exposes the active area in a second direction different from the first direction. The fourth conductive ions are implanted to form a threshold implant region, and then the second photoresist layer is removed.

Method for cell pass transistor design in DRAM process

The present invention provides a method of forming a contact hole of a DRAM on a semiconductor wafer. The semiconductor wafer comprises a substrate, a conductive layer positioned in a predetermined area of the substrate and a dielectric layer positioned on the surface of the substrate and covering the conductive layer. The method comprises forming an amorphous silicon ( &agr;-Si) layer with an opening on the surface of the dielectric layer wherein the opening is positioned directly above the conductive layer and penetrates to the surface of the dielectric layer, forming a polysilicon layer uniformly on the surface of the amorphous silicon layer and performing a dry etching process to form a contact hole in the dielectric layer, the amorphous silicon layer and the polysilicon layer being used as a hard mask, the contact hole penetrating through the dielectric layer down to the surface of the conductive layer. The polysilicon layer is formed by performing a hemi-spherical grain (HSG) process to improve the resolution limit of the optical exposure tool of the lithographic process.

Method of forming a contact hole in a semiconductor wafer

A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

Method for forming semiconductor dielectric layer

A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of the memory cell transistor. A first conductive layer then covers the insulation layer and fills into the contact opening, with the first conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first conductive layer. A second electrically conductive layer is then formed and patterned to form a recess substantially above the location of the contact opening in the insulation layer. A layer of HSG&mdash;Si then covers the surface of the second conductive layer and the surface of the recess, and the HSG&mdash;Si layer and the second conductive layer are patterned to form the bottom electrode of the capacitor. The recess and its covering HSG&mdash;Si layer increase the effective surface area of the bottom electrode of the capacitor.

Growing community of inventors

Hsinchu, Taiwan

Kun-Chi Lin