Lsi Logic Corporation

Xilinx, Inc.

Maxim Integrated Products, Inc.

Kumar Nagarajan

Zafer S Kutlu

Jerome Chandra Bhat

Raghunandan Chaware

Sarathy Rajagopalan

Mukul Joshi

Shirish Shah

Satbir Madra

Kishor V Desai

Arkadii V Samoilov

Chok J Chia

Kai Chieh Liu

Nicole Dorene Kerness

Leilei Zhang

Aritharan Thurairajaratnam

Christopher Francis Edwards

John Pierre McCormick

Farshad Ghahghahi

Ivor G Barber

Anand K Chamakura

Leah Miller

Edwin M Fulcher

Anand Govind

Yi-Sheng Anthony Sun

Dan G Allen

Yong L Xu

Kong Weng Lee

Seshasayee S Ankireddi

Richard I Olsen

Ronilo Boja

Seng Sooi Lim

Dong P Kim

Nael Zohni

Seshasayee Gaddamraja

S Gabriel R Dosdos

Stan Mihelcic

Yogendra Ranade

Ken Wang

Xiansong Chen

Laurene Yip

Thomas Evans

An optical package containing optical sensor/detector pairs co-housed with a non-optical sensor and processes for fabricating the optical package are described herein. Traditional package structures require the use of clear mold compounds to protect the sensitive dies, but such compounds degrade with time and temperature. The optical package described herein uses a special glass top cover that is transparent in the entire electro-magnetic spectral region required by the contained dies.

Structure and method for hybrid optical package with glass top cover

An optical sensor is described that includes a light emitter and a photodetector assembly directly attached to a transparent substrate. In one or more implementations, the optical sensor comprises at least one light emitter and a photodetector assembly (e.g., photodiodes, phototransistors, etc.). The light emitter(s) and the photodetector assembly are directly mounted (e.g., attached) to a transparent substrate.

Optical sensor having a light emitter and a photodetector assembly directly mounted to a transparent substrate

Embedded die packages are described that employ one or more substrate redistribution layers (RDL) to route electrode nodes and/or for current redistribution. In one or more implementations, an integrated circuit die is embedded in a copper core substrate. A substrate RDL contacts a surface of the embedded die, with at least one via (e.g., thermal via) in contact with the surface RDL to furnish electrical interconnection between the embedded die and an external contact. Additional substrate RDL or WLP RDL can be incorporated into the package to provide varying current distribution between the embedded die and external contacts.

Embedded die redistribution layers for active device

A semiconductor package device, electronic device, and fabrication methods are described that include at least one sacrificial contact pad as a portion of the semiconductor package device for preventing and reducing stress on the semiconductor package device and increasing board level reliability. In implementations, the semiconductor package device includes a lead frame substrate including at least one lead frame contact pad and at least one sacrificial contact pad, an integrated circuit device electrically coupled to the lead frame substrate, and an encapsulation layer that encapsulates the lead frame substrate and the integrated circuit device. In implementations, one process for fabricating the semiconductor package device includes placing an integrated circuit device on a lead frame substrate, where the lead frame substrate includes at least one lead frame contact pad and at least one sacrificial contact pad, and encapsulating the integrated circuit device and the lead frame substrate with an encapsulation layer.

Sacrificial pad on semiconductor package device and method

A wafer level optical device, system, and method are described that include a substrate, an electronic device disposed on the substrate, an illumination source disposed on the electronic device, an enclosure disposed on the substrate, where the enclosure includes at least one optical surface and covers the electronic device and the illumination source, and at least one solder ball disposed on a side of the substrate distal from the electronic device. In implementations, a process for using the wafer level optical device and lens-integrated package system that employ the techniques of the present disclosure includes receiving a substrate, placing an electronic device on the substrate, placing an illumination source on the electronic device, and placing an enclosure on the substrate, where the enclosure covers the electronic device and the illumination source, and the enclosure and a wall structure form a first compartment and a second compartment.

Wafer level lens in package

An optical sensor device, system, and method are described that include a substrate, an electronic device disposed on the substrate, a molding layer, a lens, and a light-emitting diode (LED) package disposed on the substrate and at least partially over the sensor and molding layer. The LED package can include an LED substrate, an LED, a lens disposed on the LED, and electrical interconnections for coupling the LED to the substrate. In implementations, a process for fabricating the optical sensor device includes backgrinding a sensor die to a slim profile; attaching the sensor die onto a substrate; placing a molding layer on the sensor die; forming a lens on the molding layer; and placing an assembled light-emitting diode package on the substrate and at least partially over the sensor die and molding layer, where the assembled light-emitting diode package includes a 3D substrate.

Stacked LED for optical sensor devices

In one or more embodiments, a semiconductor structure is provided that includes a plurality of interposer dice on an un-singulated segment of a semiconductor wafer. Scribe lanes circumscribing each of the plurality of interposer dice have widths of at least 2.5% of the width of each interposer die. Each interposer die includes a first contact array formed on a first side of the interposer die, a plurality of vias formed through the interposer die, one or more wiring layers formed on the first side of the interposer die and electrically coupling the first contact array to the plurality of vias, and a second contact array formed on a second side of the interposer die and electrically coupled to the plurality of vias.

Semiconductor structure and method for interconnection of integrated circuits

Integrated circuit packaging devices and methods are disclosed. An embodiment package lid is formed from a single piece of material. The lid includes a planar rectangular main body having a bottom surface, and a leg disposed at each corner of the main body and within a perimeter of the main body. Each leg has a wall projecting downwardly from the main body and a non-planar bottom surface disposed at a bottom of the wall. The non-planar bottom surface of the leg faces a same direction as the main body bottom surface.

Integrated circuit packaging devices and methods

In one embodiment, an interposer resistant to warping is provided. The interposer includes a semiconductor body having a first contact array included on a first side of the semiconductor body. Vias are formed through the semiconductor body. One or more wiring layers are included on the first side of the semiconductor body. The wiring layers electrically couple each contact of the first contact array to a respective one of the vias. Contacts of a second contact array, included on a second side of the semiconductor body, are respectively coupled to the vias. A stabilization layer is included on the second side of the semiconductor body. The stabilization layer is configured to counteract stresses exerted on a front side of the interposer due to thermal expansion of wiring layers.

A semiconductor device includes a semiconductor die and a plurality of lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes a plurality of metal layers and a plurality of dielectric layers. One of the metal layers includes a plurality of contact pads corresponding to the plurality of lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having a plurality of respective openings for the contact pad. A plurality of respective copper posts is disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the plurality of lead-free solder bumps and the plurality of copper posts.

Lead-free structures in a semiconductor device

An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.

Integrated circuit assembly having vented heat-spreader

A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Method of implementing a capacitor in an integrated circuit

An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.

Circuit for and method of implementing a capacitor in an integrated circuit

The present invention relates to a lid for an integrated circuit. According to one embodiment, an integrated circuit having a lid comprises a substrate having a flat surface and extending a first length and a lid having a recess and a foot portion. The lid generally has a second length shorter than the first length, and is positioned on the flat surface of the substrate. Finally, a bonding agent is positioned on the flat surface adjacent the foot portion of the lid. According to an alternate embodiment, a second component is positioned on the substrate outside the foot portion, and an adhesive seal is positioned on the substrate adjacent the foot and covering the component. A method of securing a lid to an integrated circuit is also disclosed.

Integrated circuit having a lid and method of employing a lid on an integrated circuit

An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.

Growing community of inventors

San Jose, CA, United States of America

Kumar Nagarajan