Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuei-Shun Chen

Chia-Chu Liu

Ru-Gun Liu

Yung-Sung Yen

Shih-Chi Fu

Chi-Kang Chang

Meng-Wei Chen

Tsai-Sheng Gau

Chung-Ming Wang

Chun-Kuang Chen

Wei-Liang Lin

Yuan-Hsiang Lung

Ta-Ching Yu

Shau-Lin Shue

Chin-Hsiang Lin

Chung-Ju Lee

Chia-Tien Wu

Yung-Hsu Wu

Ya Hui Chang

Hua-Tai Lin

Yu-Lun Liu

Chih-Hsiung Peng

Chao-Cheng Chen

Yu-Tien Shen

Cheng-Cheng Kuo

Chiang Mu-Chi

Yan-Tso Tsai

Ching-Yu Chang

Po-Chung Cheng

Chi-Hung Liao

Chi-Cheng Hung

Tzong-Sheng Chang

Fei-Gwo Tsai

Jui-Ping Chuang

Kai-Hsiung Chen

Ying-Hao Su

Hsueh-Yi Chung

Wei-Ti Hsu

Yu-Ching Wang

Long-Yi Chen

Jia-Hong Chu

Hsin-Chin Lin

Chi-Wen Hsieh

Chih-Wei Hsu

Li-Te S Lin

Wei-Hao Wu

Hua Feng Chen

Chia-Ping Chiang

Yung-Cheng Chen

Ya-Wen Yeh

Yu Lun Liu

Shiao-Chian Yeh

Chi-Wen Lai

Yun-Lin Wu

Chia-Ching Liang

Tsung-Lin Yang

Yen-Ming Chen

Shih-Ming Chang

Ken-Hsien Hsieh

Chih-Yuan Ting

Chien-Wei Wang

Min-Yann Hsieh

Yu-Chung Su

Chia-Hsiang Lin

Tzu-Chun Lo

Ching-Che Tsai

Po-Hsueh Li

Jeng-Shiun Ho

Min-Hung Cheng

Hong-Jang Wu

Hsiao-Wei Su

Chie-Chieh Lin

Chien-Ping Hung

Li-Jui Chen

Ziwei Fang

Ryan Chia-Jen Chen

Tzung-Chi Fu

Chia-Ying Lee

Min-Chang Liang

Yi-Shien Mor

Mu-Chi Chiang

Joy Cheng

Chih-Yang Yeh

Burn-Jeng Lin

Fu-Jye Liang

Hsiao-Tzu Lu

Kuan-Hsin Lo

Chen-Hau Wu

Wei-De Ho

Li-Yen Lin

Shang-Wern Chang

Sheng-Yu Chang

Lawrence Lin

Yung-cheng Chen

Hong-Yuan Chu

Shyue-Sheng Lu

Han-Hsun Chang

Hsiang-Yu Su

Yun-Heng Tseng

Ming-Sen Tung

A method of fabricating a semiconductor device includes generating at least one photomask based on a layout and forming a plurality of active patterns on a substrate, using the at least one photomask. The layout includes a plurality of first patterns that extend parallel to each other in a first direction on a low-density region of the layout and a plurality of second patterns that extend parallel to each other in the first direction on a high-density region of the layout. The forming of the plurality of active patterns includes using the first patterns and the second patterns of the layout to respectively form a plurality of first active patterns and a plurality of second active patterns on the substrate.

Method and structure for mandrel and spacer patterning

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

Pattern fidelity enhancement

In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Method of manufacturing a semiconductor device and semiconductor device

A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Method of fabricating reticle

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

A method includes forming a first mandrel pattern and a second mandrel pattern. The first mandrel pattern includes at least first and second mandrels for a mandrel-spacer double patterning process. The second mandrel pattern includes at least a third mandrel inserted between the first and second mandrels. The first mandrel pattern and the second mandrel pattern include a same material. The first and second mandrels are merged together with the third mandrel to form a single pattern.

A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Method for improving circuit layout for manufacturability

The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Method of fabricating field effect transistor having non-orthogonal gate electrode

A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

Pattern fidelity enhancement with directional patterning technology

A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.

A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.

Growing community of inventors

Hsinchu, Taiwan

Kuei-Shun Chen