United Silicon Incorporated

United Microelectronics Corp.

Kuan-Yang Liao

Chih-Ning Wu

Wei-Tsun Shiau

Cheng-Tung Huang

Chung-Ju Lee

Po-Chao Tsao

Ming-Tsung Chen

Yu-Lan Chang

Chang-Chi Huang

Yi-Yiing Chiang

Yi-Cheng Liu

Charlie C J Lee

Wen-Shiang Liao

Jiunn-Ren Hwang

Bang-Chiang Lan

Tzu-Yun Chang

Wen-Chi Chen

Alex Liu

A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

Fabricating method for a metal oxide semiconductor transistor

A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel

A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

Method of manufacturing semiconductor MOS transistor device

The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.

Fin field effect transistor and method for manufacturing fin field effect transistor

A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.

Method of cleaning wafer and method of manufacturing gate structure

Metal oxide semiconductor transistor

A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.

Method of removing spacers and fabricating MOS transistor

First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

Method of manufacturing MOS transistors

A method of manufacturing a DRAM capacitor comprises the steps of providing a semiconductor substrate having a source/drain region thereon, and then forming an insulating layer over the substrate. Next, a storage node opening that exposes the source/drain region is formed in the insulating layer, and then a conductive layer is formed above the storage node opening and the insulating layer. Thereafter, porous insulating material is deposited over the first conductive layer. The porous material includes porous oxide, NanoPorous Silica or Xerogel Sol-Gel, for example. Subsequently, the porous insulating layer is used as a mask to carry out a plasma-etching operation so that a portion of the conductive layer is etched away to form a plurality of long and narrow crevices. Hence, a fork-shaped conductive layer is formed. The fork-shaped first conductive layer serves as the lower electrode of a capacitor. Finally, the porous insulating layer is removed, and then the dielectric layer and the upper electrode of a capacitor are sequentially formed over the fork-shaped structure.

Method of manufacturing DRAM capacitor

A method of fabricating dual damascene structure. A substrate having devices and a defined conductive layer is provided. A dielectric layer and a hard mask material layer are formed respectively over the substrate. An opening is defined within the hard mask material layer. Because of the different selectivity of the hard mask material layer and the dielectric layer, a trench is formed within the dielectric layer by defining the hard material mask layer and a portion of dielectric layer until the conductive layer is exposed. The cross shape of the trench has a wider opening and a narrower bottom. A metal layer is then formed and the trench is filled up with the metal layer. The process of dual damascene structure is accomplished..

Method of fabricating dual damascene structure using a hard mask

A method for fabricating a crown capacitor is able to form a deep UV photoresist layer having a cylindrical structure by using only one mask. A conductive layer, the main structure of a bottom electrode, is formed on the sidewall of the deep UV photoresist layer by performing a silylation process. A fairly small and high cylindrical structure is formed by the invention, so that the crown capacitor can be used in DRAM having a storage capacity higher than 64 MB. Also, there is no problem of registration because only one mask is used.

Method to form crown capacitor for high density DRAM

A method of fabricating an opening with a deep ultra-violet photoresist layer. An insulating layer is formed on a substrate having a device structure. A deep ultra-violet photoresist layer with a first opening is formed on the insulating layer and a hard mask layer is then formed on the surface and the sidewalls of the deep ultra-violet photoresist layer. The first opening is used to pattern the insulating layer to form a second opening within the insulating layer wherein the hard mask layer is to protect the deep ultra-violet photoresist layer. The deep ultra-violet photoresist layer and the hard mask layer are removed to expose the insulating layer and a desired opening is thus accomplished.

Method of fabricating an opening with deep ultra-violet photoresist

A method for manufacturing a MOS device with multiple threshold voltages is provided. The method comprises providing a substrate. A shallow trench isolation structure is formed in the substrate. The top surface of the shallow trench isolation structure is higher than surface of the substrate. An active region which is surrounded by the shallow trench isolation structure is defined in the substrate. A first process of ion implantation is performed on the substrate except a portion of the substrate under the shallow trench isolation structure. A first spacer is formed on the sidewall of a portion of the shallow trench isolation structure above the substrate in the active region. A second process of ion implantation is performed on the substrate except a portion of the substrate under the shallow trench isolation structure and the first spacer.

Method for manufacturing a MOS device with multiple threshold voltages

A buried channel vertical double-diffusion MOS (buried channel VDMOS) device comprising a substrate, a drain region, a gate region, a source region and a channel region. The drain region is located above the substrate and the gate region is above the substrate surface. The source region is located between two neighboring gates in the substrate. The channel region is located above the drain region separated from the gate by a gate-insulating layer. The channel region further includes a main region, a buried channel region, a first region and a second region. The buried channel region is located below the gate-insulating layer. The buried channel region is impurity-doped so that the threshold voltage of the buried channel VDMOS device can be adjusted. The first region is located in the substrate between two neighboring gates, next to the drain region with portion of it extending into the region underneath the gate. The second region is located below the source region and directly under the first region, but the second region does not have direct contact with the source region.

Growing community of inventors

Hsinchu, Taiwan

Kuan-Yang Liao