Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Kuan-Lun Chang

Ruey-Hsin Liu

Chih-Min Chiang

Jun-Lin Tsai

Tsyr-Shyang Liou

Chuan-Ying Lee

Jian-Hsing Lee

Denny Tang

Yi-Hsun Wu

Chun-Lin Tsai

Bing-Yue Tsui

Chun-Hon Chen

Tsyr Shyang

A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.

Structure having a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology

A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.

High density MIM capacitor structure and fabrication process

A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology

A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

Semiconductor layout structure for ESD protection circuits

A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug. This is accomplished via photolithographic and selective dry definition procedures, and a second chemical mechanical polishing procedure, resulting in a filled, deep trench opening exhibiting a smooth top surface topography.

During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

Elimination of implant damage during manufacture of HBT

A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.

Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions

A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the CMOS and bipolar devices, such as the creation of an N type buried layer, used in one region for isolation of PFET devices, and used in a second region, of the semiconductor substrate, as a subcollector region, for the bipolar device. Features of the BiCMOS process include the formation of N well, and P well regions, for CMOS device, as well as the use of an epitaxial silicon layer, to allow optimum bipolar characteristics to be achieved.

Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer

A bipolar junction transistor structure and method of forming the bipolar junction transistor structure comprising an intrinsic base surrounded by a base link and an extrinsic base surrounding the base link. An emitter is formed above the base. The extrinsic base, base link, and intrinsic base are formed using ion implantation. A single layer of doped polysilicon is used to provide the doping source for the emitter and a collector contact. Silicide contacts to the emitter, collector, or base are not required or used.

Method for forming a bipolar junction transistor

A new method of forming simultaneously both shallow and deep trenches is described. A pad oxide layer is provided over a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A silicon dioxide layer is deposited overlying the silicon nitride layer. A photoresist mask is formed over the silicon dioxide layer wherein the photoresist mask has a first opening having a first width and a second opening having a second width and wherein the second width is larger than the first width. Trench openings are etched through the silicon dioxide, silicon nitride, and pad oxide layers to the underlying semiconductor substrate within the first and second openings. The photoresist mask is removed. The substrate is etched into through the trench openings to form first and second trenches wherein the first trench within the first opening having the first width is a shallow trench having a first depth and wherein the second trench within the second opening having the second width is a deep trench having a second depth greater than the first depth completing the formation of shallow and deep trenches simultaneously in the fabrication of an integrated circuit.

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Hsin-Chu, Taiwan

Kuan-Lun Chang