Ememory Technology Inc.

Kuan-Hsun Chen

Ming-Shan Lo

Ting-Ting Su

Chih-Wei Chen

Chun-Hung Lu

Ping-Yu Kuo

A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.

Method of programming nonvolatile memory cell

A non-volatile memory cell is disclosed. A select gate transistor, a following gate transistor, and an antifuse varactor are coupled in series on an active area. The following gate transistor is disposed between the select gate transistor and the antifuse varactor. A first ion well and a second ion well having the first conductivity type are provided in the active area. The following gate transistor partially overlaps with the first ion well. The second ion well has a doping concentration that is smaller than that of the first ion well.

Nonvolatile memory cell capable of improving program performance

A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.

Single poly nonvolatile memory device

A one time programming non-volatile memory cell includes a first floating gate transistor with a single gate structure, an isolation transistor, and a select transistor. A first terminal of the first floating gate transistor is connected with a second control line. A floating gate of the first floating gate transistor is in a floating state. A first terminal of the isolation transistor is connected with a second terminal of the first floating gate transistor. An isolation gate of the isolation transistor is connected with an isolation line. A first terminal of the select transistor is connected with a second terminal of the isolation transistor. A second terminal of the select transistor is connected with a first control line. A select transistor of the select transistor is connected with a word line.

Growing community of inventors

Tainan, Taiwan

Kuan-Hsun Chen