Taiwan Semiconductor Manufacturing Comp. Ltd.

Ku-Feng Yang

Wen-Chih Chiou

Tsang-Jiuh Wu

Yung-Chi Lin

Chen-Hua Douglas Yu

Weng-Jin Wu

Hsin-Yu Chen

Ming-Tsu Chung

Yi-Hsiu Chen

Jing-Cheng Lin

Hung-Pin Chang

Hong-Ye Shih

Chen-Yu Tsai

Hung-Jung Tu

Lin-Chih Huang

Tasi-Jung Wu

Shin-Puu Jeng

Yuan-Hung Liu

Jiung Wu

Hsiao Yun Lo

Ebin Liao

Chia-Yin Chen

HsiaoYun Lo

Jung-Chih Hu

Pei-Ching Kuo

Kuan-Liang Lai

Wei-Cheng Wu

Tsung-Ding Wang

Li-Han Hsu

Jun-Lin Yeh

Szuya Liao

Yen-Hung Chen

Cheng-Chun Tsai

Kuan-Kan Hu

Yin-Hua Chen

Shau-Lin Shue

Chi On Chui

Chia-Lin Yu

Hsin-Hsien Lu

Kuang-Wei Cheng

Kewei Zuo

Wei-Yen Woon

Chen-Fong Tsai

Han-De Chen

Ming-Chung Sung

Fu-Chi Hsu

Jing-Chen Lin

Chu-Sung Shih

Tsung-Kai Chiu

A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.

Metal features of a semiconductor device and methods for forming the same

A semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece, wherein the outlet of the conduit is positioned above the major surface of the semiconductor workpiece by a vertical distance.

Apparatus and method for wafer pre-wetting

A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Semiconductor structure comprising dummy feature interposed between the bonding connectors

A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.

Plating apparatus for plating semiconductor wafer and plating method

Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Bonding and isolation techniques for stacked transistor structures

A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.

Heterogeneous dielectric bonding scheme

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Method of forming semiconductor device having backside interconnect structure on through substrate via

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

Interconnect structure and method of forming same

A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

Isolation bonding film for semiconductor packages and methods of forming the same

A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.

Semiconductor device and method

A semiconductor apparatus and methods of processing a semiconductor workpiece are provided. The semiconductor apparatus for pre-wetting a semiconductor workpiece includes a process chamber, a workpiece holder disposed within the process chamber to hold the semiconductor workpiece, a pre-wetting fluid tank disposed outside the process chamber and containing a pre-wetting fluid, and a conduit coupled to the pre-wetting fluid tank and extending into the process chamber. The conduit delivers the pre-wetting fluid from the pre-wetting fluid tank out through an outlet of the conduit to wet a major surface of the semiconductor workpiece comprising a plurality of recess portions.

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

TSV structure and method forming same

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Through-substrate vias with improved connections

Growing community of inventors

Dali, Taiwan

Ku-Feng Yang