Intel Corporation

Micron Technology Incorporated

Intel Ndtm US LLC

Kristopher H Gaewsky

Aliasgar S Madraswala

Yogesh B Wakchaure

Purval Shyam Sule

Trupti Bemalkhedkar

Xin Guo

Shantanu R Rajwade

Robert Frickey

Iwen Chao

Dheeraj Srinivasan

Charan Srinivasan

Naveen Vittal Prabhu

Joseph F Doller

Leonard Aaron Turcios

Nehul N Tailor

Quan H Ngo

Pranav Kalavade

Rohit Sudhir Shenoy

Bharat M Pathak

Xin Sun

Heonwook Kim

Siddhanth Munukutla

Jason H Culp

Tanya Wanchoo

Brian C Romo

Byeongkyu Cho

Kevin K Liou

Christian Mion

Noah Mebane

For NAND devices having a zero voltage program state as a result of a preconditioning operation, detecting the status of the zero voltage program state is important for customers to quickly validate their component and SSD flows to improve NAND retention and reliability after assembly and die level re-work. A zero voltage program state detection operation quickly determines the validity of the zero voltage program state of a NAND page of a NAND device. The detection operation includes reading a NAND page with reference voltages that delimit a predetermined acceptable range of voltage levels below and above a zero threshold voltage. If NAND memory cells having threshold voltage levels that fall below or above the acceptable voltage levels exceed a predetermined failed bytes limit for the NAND page, the zero voltage program state is invalid.

Zero voltage program state detection

Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.

Read latency reduction for partially-programmed block of non-volatile memory

In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

Method and apparatus for improving write uniformity in a memory device

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.

SSD with reduced secure erase time and endurance stress

Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory device

Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.

One check fail byte (CFBYTE) scheme

In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.

Method and apparatus for dynamically determining start program voltages for a memory device

Technology for a NAND memory is described. The NAND memory can include a first-type dedicated memory block. The NAND memory can include a second-type dedicated memory block. The NAND memory can include logic to perform a data operation on the first-type dedicated memory block using a first first-type access mode. The NAND memory can include logic to perform a data operation on the variable-type memory block using a second first-type access mode.

Memory block access modes for a storage device

Systems, apparatuses and methods may provide for technology to identify an initial data band that spans a plurality of memory dies and revectors the plurality of memory dies to stagger the initial data band across a plurality of modified data bands. In one example, the revector of the plurality of memory dies is conducted independently of any block defects detected in the initial data band.

Solid state drive physical block revectoring to improve cluster failure rates

In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.

Method and apparatus for avoiding bus contention after initialization failure

Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.

Error corrected pre-read for upper page write in a multi-level cell memory

An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Lower page read for multi-level cell memory

Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Growing community of inventors

El Dorado Hills, CA, United States of America

Kristopher H Gaewsky