Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec Vzw

Krishna Kumar Bhuwalka

Gerben Doornbos

Matthias Passlack

Martin Christopher Holland

Ken-Ichi Goto

Richard Kenneth Oxland

Carlos H Diaz

Georgios Vellianitis

Mark Van Dal

Wen-Chin Lee

Ching-Ya Wang

Blandine Duriez

Yi-Ming Sheu

Amey Mahadev Walke

Anne Vandooren

Yee-Chaung See

Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

Vertical tunnel field effect transistor (FET)

Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.

Heterostructures for semiconductor devices and methods of forming the same

A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.

Semiconductor device channel system and method

A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.

Fin tunnel field effect transistor (FET)

A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.

Method for forming counterdoped semiconductor device comprising first epitaxial layer and second epitaxial layer formed over first epitaxial layer having conductivity type different than second epitaxial layer

The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.

Intra-band tunnel FET

A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.

Tunnel field-effect transistor

A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.

FinFET with channel backside passivation layer device and method

Various heterostructures and methods of forming heterostructures are disclosed. A structure includes a substrate, a template layer, a barrier layer, and a device layer. The substrate comprises a first crystalline material. The template layer comprises a second crystalline material, and the second crystalline material is lattice mismatched to the first crystalline material. The template layer is over and adjoins the first crystalline material, and the template layer is at least partially disposed in an opening of a dielectric material. The barrier layer comprises a third crystalline material, and the third crystalline material is a binary III-V compound semiconductor. The barrier layer is over the template layer. The device layer comprises a fourth crystalline material, and the device layer is over the barrier layer.

A method comprises growing a channel layer comprising a first channel region and a second channel region, depositing a first hard mask layer over the channel layer, patterning the first hard mask layer, applying a first delta doping process to the first channel region to form a first delta doping layer over the first channel region, depositing a first cap layer over the first delta doping layer, depositing a second hard mask layer over the channel layer, wherein the first cap layer is embedded in the second hard mask layer, patterning the second hard mask layer and the first hard mask layer to expose the second channel region, applying a second delta doping process to the second channel region to form a second delta doping layer over the second channel region and applying a first diffusion process to the first delta doping layer and the second delta doping layer.

Multiple-threshold voltage devices and method of forming same

A multi-threshold voltage (V) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.

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Asansol, India

Krishna Kumar Bhuwalka