Renesas Electronics Corporation

Renesas Technology Corp.

Kouhei Sugihara

Hidekazu Oda

Hirokazu Sayama

Kazunobu Ohta

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000&#xb0; C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

A gate insulating film () and a gate electrode () of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (). Using the gate electrode () as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode () is amorphized. Subsequently, a silicon oxide film () is provided to cover the gate electrode (), at a temperature which is less than the one at which recrystallization of the gate electrode () occurs. Thereafter, thermal processing is performed at a temperature of about 1000&#xb0; C., whereby high compressive residual stress is exerted on the gate electrode (), and high tensile stress is applied to a channel region under the gate electrode (). As a result, carrier mobility of the nMOS transistor is enhanced.

A gate insulating film () and a gate electrode () of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (). Using the gate electrode () as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode () is amorphized. Subsequently, a silicon oxide film () is provided to cover the gate electrode (), at a temperature which is less than the one at which recrystallization of the gate electrode () occurs. Thereafter, thermal processing is performed at a temperature of about 1000&#xb0; C., whereby high compressive residual stress is exerted on the gate electrode (), and high tensile stress is applied to a channel region under the gate electrode (). As a result, carrier mobility of the NMOS transistor is enhanced.

A gate insulating film () and a gate electrode () of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (). Using the gate electrode () as a mask, n-type dopants having a relatively large mass number (or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode () is amorphized. Subsequently, a silicon oxide film () is provided to cover the gate electrode (), at a temperature which is less than the one at which recrystallization of the gate electrode () occurs. Thereafter, thermal processing is performed at a temperature of about 1000&#xb0; C., whereby high compressive residual stress is exerted on the gate electrode (), and high tensile stress is applied to a channel region under the gate electrode (). As a result, carrier mobility of the nMOS transistor is enhanced.

A method of manufacturing a semiconductor device is provided which can suppress leakage current increases by making into silicide. Impurity that suppresses silicide formation reaction (suppression impurity), such as germanium, is introduced into source/drain regions () from their upper surfaces. In the source/drain regions (), a region shallower than a region where the suppression impurity is distributed () is made into silicide, so that a silicide film () is formed in the source/drain regions (). Thus, by making the region shallower than the region () into silicide, it is possible to suppress that silicide formation reaction extends to the underside of the region to be made into silicide. This enables to reduce the junction leakage between the source/drain regions () and a well region.

Manufacturing method of semiconductor device

A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer on the gate insulating film, implanting ions into the polysilicon layer, patterning the polysilicon layer to form a gate electrode, annealing the gate electrode, and siliciding an upper portion of the gate electrode to form a silicide layer that has a lower portion facing the gate electrode and an upper portion opposite to the lower portion, the upper portion of the silicide layer being wider than the lower portion. A total dose of ions implanted during the step of implanting is 6&times;10 /cm or larger.

Growing community of inventors

Tokyo, Japan

Kouhei Sugihara