Murata Manufacturing Co., Ltd.

Kouassi Sebastien Kouassi

Simon Edward Willard

Sinan Goktepeli

Eric S Shapiro

Jeffrey A Dykstra

Jean-Luc Erb

Kazuhiko Shibata

Shishir Ray

Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit/device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and/or junction fully contains a projection of a planar surface area of the first circuit and/or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit/device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.

Back-gate effect control via doping

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San Diego, CA, United States of America

Kouassi Sebastien Kouassi