Intel Corporation

Exo Imaging, Inc.

Kooi Chi Ooi

Bok Eng Cheah

Jackson Chung Peng Kong

Shanggar Periaman

Jenny Shio Yin Ong

Seok Ling Lim

Yen Hsiang Chew

Ping Ping Ooi

Min Suet Lim

Khang Choong Yong

Divya Vijayaraghavan

Denica N Larsen

Michael P Skinner

Lady Nataly Pinilla Pico

Yang Liang Poh

Thorsten Meyer

Hans-Joachim Barth

Eng Huat Goh

Shekoufeh Qawami

Bernd Waidhas

Boon Ping Koh

Howe Yin Loo

Casey Baron

Naissa Conde

Paik Wen Ong

Mengjie Yu

Dirk Plenkers

Howard L Heck

Jiun Hann Sir

Stephen H Hall

Yong She

Stephen H Hall, Jr

Jiamiao Tang

Junfeng Zhao

Teong Guan Yew

Mark A Schaecher

Chan Kim Lee

Teong Keat Beh

Chia Chuan Wu

Kok Hou Teh

Ridza Effendi Abd Razak

Eric C Gantner

Lee Fueng Yap

Li Wern Chew

Kheng Tat Mar

The present disclosure generally relates to a printed circuit board assembly that may include a circuit board having a first surface and an opposing second surface. The printed circuit board assembly may also include a first interconnect barrel disposed in the circuit board. The first interconnect barrel may have a first length extending between the first surface and the second surface. The first interconnect barrel may include a first section, and may further include a second section spaced apart from the first section by a first gap having a first depth extending partially through the first length. The printed circuit board assembly may further include a first conductive trace coupled to the first section and a second conductive trace coupled to the second section at a first terminal.

Vertical interconnect design for improved electrical performance

The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

Integrated bridge frame for package substrate

According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

Semiconductor package with hybrid mold layers

Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.

Molded silicon interconnects in bridges for integrated-circuit packages

An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

Integrated bridge for die-to-die interconnects

A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Encapsulated vertical interconnects for high-speed applications and methods of assembling same

An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

Substrate with gradiated dielectric for reducing impedance mismatch

The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 &#x3bc;m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Devices and methods for signal integrity protection technique

Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

Methods and apparatus to improve data training of a machine learning model using a field programmable gate array

Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

Embedded reference layers for semiconductor package substrates

Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.

Evaluating risk factors of proposed vehicle maneuvers using external and internal data

Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

Methods and apparatus for allocating a workload to an accelerator using machine learning

The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

Vertical die-to-die interconnects bridge

The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.

Electrical shield for stacked heterogeneous device integration

According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.

Hybrid ball grid array package for high speed interconnects

Growing community of inventors

Glugor, Malaysia

Kooi Chi Ooi