International Business Machines Corporation

Cornell Research Foundation Inc.

Endicott Interconnect Technologies, Inc.

International Business Corporation

I3 Electronics, Inc.

Konstantinos I Papathomas

Donald Seton Farquhar

Voya Rista Markovich

John M Lauffer

Alfred Viehbeck

Jeffrey Curtis Hedrick

Robert Maynard Japp

Mark David Poliks

Niranjan Mohanlal Patel

Gary A Johansson

Jeffrey T Gotro

Jane M Shaw

Brian Eugene Curcio

David W Wang

Bernd Karl Appelt

John Joseph Konrad

Ali Afzali-ardakani

Thomas R Miller

William J Summa

Michael A Gaynes

Stephen L Buchwalter

Anilkumar Chinuprasad Bhatt

Roy H Magnuson

Gerald Walter Jones

John A Welsh

Stephen Joseph Fuerniss

William Joseph

Hung Manh Dang

Peter Alfred Gruber

Jeffrey Donald Gelorme

Luis Jesus Matienzo

Claudius Feger

James Warren Wilson

Douglas Oliver Powell

William E Wilson

James Robert Wilcox

Rabindra N Das

Stephen L Tisdale

Christina Marie Boyko

Michael Joseph Klodowski

Timothy Leroy Wells

Ashit A Mehta

Steve Harris Weingart

Frederic Maurer

Patrick Robert Zippetelli

Michael J Cibulsky

George Szeparowycz

Yenloan H Nguyen

Deborah Lynn Dittrich

Sampath Purushothaman

Sung Kwon Kang

George G Barclay

Benson Chan

Christopher Kemper Ober

Elizabeth F Foster

David Erle Houser

Charles Robert Davis

Ross William Keesler

Ramesh R Kodnani

Cory J Ruud

Richard Allen Day

James R Stack

Jerome J Wagner

Amarjit S Rai

Bernd Karl-Heinz Appelt

Nageshwer Rao Bantu

Joseph J Sniezek

Mary Beth Fletcher

Thomas H Lewis

Lee P Springer

Terry D Sinclair

James J McNamara

James P Paoletti

Robert L Nedbalski

A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

Electrically conductive adhesive (ECA) for multilayer device interconnects

A low loss capacitance and low loss insulating dielectric material consisting of a thermosetting resin, thermoplastic resin, a cross-linker, and containing a quantity of ferroelectric ceramic nano-particles of barium titanate within. The combined low loss insulating dielectric layer and a low loss capacitive layer resulting from the material allows one continuous layer that can form internal capacitors and permit the modifying the dielectric thickness between signal layers for impedance matching within a layer of substrate. More significantly, the applied layer of low loss capacitive materials can simultaneously act as a capacitor as well as a dielectric for separation of signal layers.

Circuitized substrate with low loss capacitive material and method of making same

An encapsulant composition. The encapsulant composition includes a resin material consisting of epoxy or cyanate ester resins, from about 1.0% by weight to about 5% by weight of the composition of a flexibilizing agent including a flexibilizer containing functional groups capable of reaction with the epoxy or cyanate ester resin during thermally induced curing, a filler material including substantially spherical or spheroidal particles such that each particle has a diameter less than about 41 microns, and a thermoplastic other than the flexibilizer. The thermoplastic is separated from the cured epoxy or cyanate ester resin. The thermoplastic includes a poly(arylene)ether. The flexibilizer includes bis(2,3-epoxy-2-methylpropyl)ether.

Encapsulant of epoxy or cyanate ester resin, reactive flexibilizer and thermoplastic

Electrically conducting adhesives having a broader selectable range of properties are provided by having random sizes of micrometer diameter range particles coated with a low melting temperature metal. The coated particles are suspended in a vehicle of a mixture of thermosetting resins together with a flux resin selected for viscosity and low shrinkage, for screen printability, for electrical and for mechanical properties over a broad range of specification conditions. The vehicle or resin system includes thermosetting cyclo-aliphatic epoxy, thermosetting phenoxy polymer and thermosetting mono-functional limonene oxide. The low temperature melting coating system for the particles includes In, Sn, and alloys such as In&#x2014;Sn, Sn&#x2014;Pb, Bi&#x2014;Sn&#x2014;In and InAg. The micrometer diameter range particles includes Cu, Ni, Co, Ag, Pd, Pt, polymer and ceramic.

Electrically conducting adhesives for via fill applications

A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Method and structure for producing Z-axis interconnection assembly of printed wiring board elements

An encapsulant composition and an electronic package. The composition includes a resin, a flexibilizing agent, and a filler material. The electronic package includes a substrate, a semiconductor chip, and a material. The semiconductor chip is mounted on an upper surface of the substrate and electrically coupled to the substrate. The material is positioned on the upper surface of the substrate and against an edge surface of the semiconductor chip. The edge surface of the semiconductor chip is substantially perpendicular to a bottom surface of the semiconductor chip. The material is the encapsulant composition.

Electronic package with epoxy or cyanate ester resin encapsulant

A method of making an encapsulant composition. The method includes: providing a first quantity of resin material of epoxy or cyanate ester resins; adding to the first quantity of resin material a second quantity of flexibilizing agent; adding to the first quantity of resin material a third quantity of filler material; blending the resin material. After adding the flexibilizing agent, adding the filler material, and blending the resin material, applying the composition to a gap between a substrate and a semiconductor chip. After applying the composition to the gap, pregelling the composition. After pregelling the composition, substantially curing the composition.

Encapsulant composition and electronic package utilizing same

A composition for use in making an encapsulant usable in the encapsulation of a semiconductor chip assembled to a substrate with C4 solder interconnections therebetween, which in turn may form part of an electronic package. The composition comprises a resin, a flexibilizing agent and a filler material.

The present invention relates to a method for providing an interconnect between layers of a multilayer circuit board. A first via extending through a total thickness of a first layer is formed. The first via is totally filled with a first solid conductive plug and an end of the first solid conductive plug includes a first contact pad that is in contact with a surface of the first layer. A second via extending through a total thickness of a second layer is formed. The second via totally filling with a second solid conductive plug and an end of the second solid conductive plug includes a second contact pad that is in contact with a surface of the second layer. The second layer is electrically and mechanically coupled to the first layer by an electrically conductive adhesive that is in electrical and mechanical contact with both the end of the first plug and the end of the second plug.

Solid via layer to layer interconnect

An electronic structure bondable to an electronic assembly, such as a chip. The electronic structure may be joined to a electronic assembly, such as a chip, by use of a structural epoxy adhesive. The electronic structure includes a mineral layer on a metallic plate, and an adhesion promoter layer on the mineral layer. The metallic plate includes a metallic substance that includes a pure metal with or without a metal coating. The metallic substance may include such substances as stainless steel, aluminum, titanium, copper, copper coated with nickel, and copper coated with chrome. The mineral layer includes a chemical compound derived from a mineral; e.g., silicon dioxide (SiO) derived from quartz. Such chemical compounds may include such substances as silicon dioxide, silicon nitride, and silicon carbide. The chemical compound may exist in either crystalline or amorphous form. The adhesion promoter may include such chemical substances as silanes, titanates, zirconates, and aluminates.

Cap attach surface modification for improved adhesion

A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.

Semiconductor device having a thermoset-containing dielectric material and methods for fabricating the same

A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

Formation of multisegmented plated through holes

A method of making an interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the method includes the steps of providing a substrate having at least one plated through hole therein, and positioning a first conductive layer and a second conductive layer over the at least one plated through hole on opposing surfaces of the substrate. The method includes positioning a layer of dielectric material thereon on the first conductive layer. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, and at least a pair of conductive layers that can carry signals, and power.

Method of making and interconnect structure

A structure and method for forming a tamper respondent electronic circuit enclosure that includes an integrated circuit structure, a mesh structure surrounding the integrated circuit structure, and a sealed enclosure surrounding the mesh structure. The mesh structure includes a layer of flexible dielectric having a first side and a second side, a screen-printed pattern of flexible electrically conductive first circuit lines forming a first resistor network on the first side, and a photo lithographically-formed pattern of flexible electrically conductive second circuit lines forming a second resistor network on the second side.

Tamper-responding encapsulated enclosure having flexible protective mesh structure

A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.

Laminate circuit structure and method of fabricating

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Endicott, NY, United States of America

Konstantinos I Papathomas