Infineon Technologies Ag

Infineon Technologies Austria Ag

Konrad Roesl

Alexander Heinrich

Oliver Eichinger

Tobias Schmidt

Michael Juerss

Kok Chai Goh

Joachim Mahler

Arthur Unrau

Kirill Trunov

Khalil Hosseini

Edmund Riedl

Peter Strobel

Horst Groeninger

Rupert Fischer

Ivan Galesic

Eduard Knauer

Peter Mederer

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Electronic device with multi-layer contact and system

A semiconductor device includes: a semiconductor die having a metal region; a substrate having a metal region; and a soldered joint between the metal region of the semiconductor die and the metal region of the substrate. One or more intermetallic phases are present throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the semiconductor die and the metal region of the substrate. The soldered joint has the same length-to-width aspect ratio as the semiconductor die.

Semiconductor device having a soldered joint with one or more intermetallic phases

A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 &#x3bc;m and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.

Preform diffusion soldering

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 &#x3bc;m and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

Batch diffusion soldering and electronic devices produced by batch diffusion soldering

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.

Method for producing electronic device with multi-layer contact

Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.

Batch process for connecting chips to a carrier

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Electronic device with multi-layer contact

A self-aligning pick-up head, a method to manufacture a pick-up head and a method of manufacturing a device are disclosed. In one embodiment a pick-up head includes a nozzle having a first end portion and a second end portion and a base tool comprising a collet head, wherein the first end portion of the nozzle is gimbaled to the base tool.

Self-aligning pick-up head and method for manufacturing a device with the self-aligning pick-up head

A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 &#x3bc;m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mmof surface area of the first main surface and heat is applied to the solder material.

Method for mounting a semiconductor chip on a carrier

A method for the planar joining of components of semiconductor devices involves coating the components with diffusion materials on their upper sides and rear sides, respectively. Subsequently, the components to be joined one on the other are introduced into a reducing atmosphere. The components are aligned and a compressive pressure is exerted on the aligned components. While heating up the components to be joined in the reducing atmosphere to a diffusion joining temperature, isothermal solidification takes place, the diffusion joining temperature lying below the melting temperature of the forming diffusion joint of the joined material.

Method for the planar joining of components of semiconductor devices and a diffusion joining structure

A semiconductor device has a circuit carrier with a number of internal contact areas is disclosed, which includes a first material with a first electrochemical potential, and a semiconductor chip with an active surface and a number of chip contact areas, which include a second material with a second electrochemical potential. Bonding wire connections are arranged between the chip contact areas and the internal contact areas of the leadframe and comprise a third material with a third electrochemical potential. The connecting points between the chip contact areas and the bonding wires and/or the connecting points between the internal contact areas and the bonding wires are coated with an anticorrosive layer.

Growing community of inventors

Teublitz, Germany

Konrad Roesl