Chartered Semiconductor Manufacturing Ltd (corporation)

National University of Singapore

Kong Hean Lee

Eng Hua Lim

Soh Yun Siah

Chong Wee Lim

Chun Hui Low

Soo Jin Chua

Kin Leong Pey

Chaw Sing Ho

Pei Ching Lee

Alex See

Kheng Chok Tee

Feng Chen

Wang Ling Goh

Peter Chew

Subramanian Balakumar

Kin-Leong Pey

Seng-Keong Victor Lim

Harianto Wong

Xian Bin Wang

R Pg Karunasiri

G Karunasiri

Zheng Zhou

A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.

Method to form shallow trench isolations

A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process. The chemical mechanical polishing process removes the polysilicon layer and forms a plug of dielectric material that fills the trench. The plug of dielectric material has a top surface that is planar with respect to the top of the silicon nitride layer.

Shallow trench isolation using TEOS cap and polysilicon pullback

A method for forming a void-free epitaxial cobalt silicide (CoSi ) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550&deg; C. and 580&deg; C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi /CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrigen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825&deg; C. and 875&deg; C. to convert the CoSi /CoSi layer to a CoSi layer. The CoSi layer can optionally be implanted with impurity ions which are subsequently diffused to form ultra-shallow junctions.

Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or &ldquo;unframed&rdquo; electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or &ldquo;unframed&rdquo; electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner. This method of forming borderless contacts with a passivating trench liner in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. In addition, the use of this invention's semi-recessed STI process scheme helps to reduce the aspect ratio of the trench, thereby aiding the filling of the trench. Therefore, with the process described herein, STI oxide seam formation is eliminated.

Partially recessed shallow trench isolation method for fabricating borderless contacts

A Method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad oxide layer, and the semiconductor substrate are patterned to form a trench having rounded corners in the isolation area. A liner oxide layer is formed over the semiconductor substrate, and a gap fill layer is formed on the liner oxide layer. An important feature of the invention is that the gap fill layer is composed of silicon oxynitride formed using a high density plasma chemical vapor deposition process. A portion of the gap fill layer over the active area can be removed using a reverse trench mask etch, and the gap fill layer is further planarized with a chemical mechanical polishing process using the liner oxide layer as chemical mechanical polishing stop.

Method for forming a shallow trench isolation using HDP silicon oxynitride

A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.

Method of making low-leakage architecture for sub-0.18 .mu.m salicided

A method to form a 'mushroom shaped' gate structure 18 22 44A 70 that increases the top gate silicide contact area and improves the salicide process, especially TiSi.sub.2 salicide. The novel upper gate extensions 44A increase the top gate surface area so that the silicide gate contacts 70 will have a low resistivity. The invention includes forming a gate stack 18 22 26 comprised of a gate oxide layer 18, a center gate portion 22 and a hard mask 26. Next, we form a first insulating layer 40 over the gate stack 22 26 18. The hard mask 26 and a first thickness of the first insulating layer 40 are removed to expose sidewalls of the center gate portion 22. A second conductive layer 44 is formed over the first insulating layer 46 and the center gate portion 22. The second conductive layer 44 is etched to form critical rounded upper gate extensions 44A on the sidewalls of the center gate portion 22. Lower rectangular sidewall spacers 52 are formed on the sidewalls of the center gate portion 22. Source/drain regions 54 are formed. A salicide process forms silicide source/drain contacts 64 and forms extra large silicided gate contacts 70 to reduce parasitic resistance.

Cmos gate architecture for integration of salicide process in sub 0.1    .

An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.

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Singapore, Singapore

Kong Hean Lee