Spansion Llc.

Fujitsu Corporation

Koji Shimbayashi

Takaaki Furuyama

Kenta Kato

Masahiro Niimi

Kenji Shibata

In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.

Capacitive element using MOS transistors

In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate, layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.

Method of manufacturing a semiconductor device

Semiconductor device and method of manufacturing the same

A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

Memory employing independent dynamic reference areas

A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

Memory employing separate dynamic reference areas

A voltage detection circuit for accurately detecting a voltage that is unaffected by fluctuation due to variations in transistor characteristics and threshold voltage. The voltage detection circuit includes a reference current generating section and a detecting section. The reference current generating section includes a voltage-controlled current source that includes a control terminal, a reference terminal and an output terminal. The reference current generating section generates an output current that serves as a reference current and output to a current mirroring circuit. The detecting section includes a number of voltage-controlled current sources each with the same configuration as the voltage-controlled current sources in the current generating section. A potential to be detected is input into the detecting section. A target potential is calculated as the set potential multiplied by the number of voltage-controlled current sources in the detecting section. When the absolute value of the potential to be detected equals the target potential, the currents in each of the voltage-controlled current sources in the detecting section is set equal to the set potential. Due to the equivalent configurations of the voltage-controlled current sources, the current flowing in the reference current generating section is balanced with, and becomes equal to the current in the detecting section. The detection is made by current comparison between the reference current output from the reference current generating section and the detection current flowing in the detecting section.

Voltage detector circuit

An access identification circuit () identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit () and/or setting a pulse width for an equalize signal EQ in an amplification control circuit () is stored in each of first and second storage sections () that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit () in response to the identification signal S and fed to the dummy load circuit () and/or the amplification control circuit (). A suitable operating condition is selected for each of the access operations.

Memory device and control method therefor

In a single data rate (SDR) mode, logic level transitions of a data condition prior-determination signal RDYO are outputted to an output terminal (O) in response to an internal clock signal CKI. A ready signal RDY is outputted in synchronization with the internal clock signal CKI following a logic level transition of the data condition prior-determination signal RDYO. In a double data rate (DDR) mode, on the other hand, a toggle signal is outputted to the output terminal (O) in correspondence with the internal clock signal CKI following a logical level transition of the data condition prior-determination signal RDYO. After the internal clock signal CKI following the logical level transition of the data condition prior-determination signal RDYO, a strobe signal DQS is outputted in synchronization with the internal clock signal CKI. The ready signal RDY is outputted at the data condition informing terminal (X) in SDR mode while, on the other hand, the strobe signal DQS is outputted at the data condition informing terminal (X) in DDR mode.

Memory device and method of controlling the same

Of bit line selection address bits A(k) to A(k+3), address bits A(k+1) and A(k+2) are subjected to exclusive OR operation with address bit A(k+3) by an address conversion circuitand when address bit A(k+3) is at high level, the address is inputted to an upper column decoderwith their logical levels inverted. In left and right areas AAand AAof eight bit lines within subarray AA, the order of selecting bit lines is switched in ascending order and descending order every four lines. With the construction of a lower pass gatethat alternately selects the left and right areas AAand AAfor each access, in continuous access within subarray and between subarrays, the distance between bit lines selected in adjacent accesses can be sufficiently secured, so that the electrical influence of a bit line accessed previously exerts no influence on a bit line accessed subsequently.

Semiconductor storage device and method of selecting bit line of the semiconductor storage device

A semiconductor memory device wherein, in continuous data reading, a notification signal to notify whether a suspend mode is entered or not is given synchronously with data output control according to an output control signal with a suspend function, and a method of controlling the device. When an output enable signal is also used as a suspend instruction, a synchronizing circuit synchronizes the output enable signal with a clock signal to output a synchronized output enable signal. This synchronized output enable signal is supplied to a ready control circuit and an output buffer circuit so that the output control of data and ready signal is performed in synchronization with the clock signal. A data terminal goes into a high impedance state in synchronization with the clock signal, which notifies transition to the suspend mode. This quickly notifies that the system bus has become open.

Semiconductor memory device and semiconductor memory device control method

This invention provides a nonvolatile semiconductor memory device including a novel memory core portion in which an influence of a parasitic element component in a memory cell information reading path is excluded in a reading operation, and novel sensing means accompanying this memory core structure, so as to achieve rapid sensing. In the memory core portion, a selected memory cell is selected by a global bit line through a local bit line and an adjacent global bit line is connected to a local bit line in a non-selected sector. A column selecting portion connects a pair of the global bit lines to a pair of data bus lines. A load portion having a load equivalent to a parasitic capacitance of a path leading from the memory cell and for supplying a reference current to a reference side is connected to a pair of the data bus lines. A current of the memory cell information is compared with the reference current by a current comparing portion and a differential current is outputted. A path load is equalized by a pair of adjacent paths so that an effect from noise is canceled, thus making it possible to achieve rapid reading.

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Kasugai, Japan

Koji Shimbayashi