Showa Denko K.k.

Toyoda Gosei Co., Ltd.

Koji Kamei

Yoshitaka Nishihara

Hisayuki Miki

Noritaka Muraki

Munetaka Watanabe

Ling Guo

Yasushi Ohno

Hironao Shinohara

Takashi Hodota

Daisuke Muto

Gaku Oriji

Yoshiaki Kageshima

Akira Miyasaka

Remi Ohba

Jun Norimatsu

Honglin Wang

Akihiro Matsuse

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 &#x3bc;m or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

SiC epitaxial wafer and method for manufacturing same

A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H&#x2014;SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 6.0 inclusions/cm, and wherein a density of large pit defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.5 defects/cmor less.

SiC epitaxial wafer containing large pit defects with a surface density of 0.5 defects/CM2 or less, and production method therefor

An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer having an impurity concentration of 1&#xd7;10cmor more, irradiating a surface of the high-concentration epitaxial layer having an impurity concentration of 1&#xd7;10cmor more with excitation light, and observing a surface irradiated with the excitation light via a band-pass filter having a wavelength band of 430 nm or less.

Evaluation method and manufacturing method of SiC epitaxial wafer

A SiC epitaxial wafer in which a SiC epitaxial layer is formed on a 4H-SiC single crystal substrate having an off angle and a substrate carbon inclusion density of 0.1 to 2.5 inclusions/cm, wherein a total density of large pit defects and triangular defects caused by substrate carbon inclusions and contained in the SiC epitaxial layer is 0.6 defects/cmor less.

Method for producing a SiC epitaxial wafer containing a total density of large pit defects and triangular defects of 0.01 defects/cm2 or more and 0.6 defects/cm2 or less

A SiC epitaxial wafer, including: a SiC substrate; and an epitaxial layer stacked on a first surface of the SiC substrate, wherein an area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is identified, and the area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is equal to or less than &#xbc; of the first surface area of the SiC substrate.

SiC substrate evaluation method and method for manufacturing SiC epitaxtal wafer

A SiC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SiC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cmand equal to or less than 10 pieces/cm.

SiC substrate, SiC epitaxial wafer, and method of manufacturing the same

A SiC wafer defect measuring method which includes a device management step of managing a defect measuring device by irradiating a reference sample made of a material having a light-emitting intensity that does not change with repeated irradiation by excitation light and which has a pattern made of recesses and/or protrusions in the surface, the irradiation by the excitation light being performed before measuring defects in a SiC wafer and under the same irradiation conditions as the measurement of the defects in the SiC wafer, and then measuring the S/N ratio of the pattern from a reflection image of the pattern.

SiC wafer defect measuring method, reference sample, and method of manufacturing SiC epitaxial wafer

A SiC epitaxial wafer having a SiC epitaxial layer formed on a SiC single crystal substrate having an offset angle of 4 degrees or less in a&#x3c;11-20&#x3e;direction from a (0001) plane. A trapezoidal defect included in the SiC epitaxial wafer includes an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow. Also disclosed is a method for manufacturing the SiC epitaxial wafer.

SiC epitaxial wafer and method for manufacturing SiC epitaxial wafer

In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.

SiC substrate evaluation method and method for manufacturing SiC epitaxial wafer

The present invention aims to enhance the light extraction efficiency of the Group III nitride semiconductor light-emitting device. The inventive Group III nitride semiconductor light-emitting device comprises a substrate; and a Group III nitride semiconductor layer including a light-emitting layer, stacked on the substrate, wherein the side face of the Group III nitride semiconductor layer is tilted with respect to the normal line of the major surface of the substrate.

Group III nitride semiconductor light-emitting device

A semiconductor light emission element () includes: a substrate (); multi-layered semiconductor layers () including a light emission layer () and layered on the substrate (); a transparent electrode () including an indium oxide and layered on the multi-layered semiconductor layers (); a first junction layer () including tantalum as a valve action metal and layered on the transparent electrode () in such a manner that a side of the first junction layer () being in contact with the transparent electrode () is a tantalum nitride layer or a tantalum oxide layer; and a first bonding pad electrode () layered on the first junction layer () and used for electrical connection with outside. This improves a bonding property of the transparent electrode or the semiconductor layer with the connection electrode and reliability of the electrodes.

Semiconductor light emission element

A semiconductor light emitting element () provided with an n-type semiconductor layer (), a light emitting layer (), a p-type semiconductor layer (), a transparent electrode (), a p-side electrode () formed on the transparent electrode, and an n-side electrode () formed on the n-type semiconductor layer. The p-side electrode has a p-side joining layer () and a p-side bonding pad electrode (), which are laminated on the transparent electrode, and the n-side electrode has an n-side joining layer () and an n-side bonding pad electrode (), which are laminated on the n-type semiconductor layer. The p-side joining layer and the n-side joining layer are configured of a mixed layer composed of TaN and Pt, and the p-side bonding pad electrode and the n-side bonding pad electrode are configured of a laminated structure composed of Pt and Au.

Semiconductor light emitting element and method for manufacturing semiconductor light emitting element

A gallium nitride-based compound semiconductor light-emitting device includes an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer of gallium nitride-based compound semiconductors which are formed in this order on a substrate, the negative electrode and the positive electrode being provided in contact with the n-type semiconductor layer and the p-type semiconductor layer, respectively. The positive electrode includes a first electrode and an over-coating layer covering the side surfaces and upper surface of the first electrode, and the area where the over-coating layer comes into contact with the p-type semiconductor layer is greater at the corner portions of the positive electrode than at the side portions thereof, per unit length of the outer edge of the first electrode.

Gallium nitride-based compound semiconductor light-emitting device with an electrode covered by an over-coating layer

This gallium nitride-based compound semiconductor light emitting device includes an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are composed of gallium nitride-based compound semiconductors and are deposited in that order on a substrate, and further includes a negative electrode and a positive electrode that are in contact with the n-type semiconductor layer and the p-type semiconductor layer, respectively, wherein the positive electrode has a translucent electrode composed of a three-layer structure including a contact metal layer that contacts at least the p-type semiconductor layer, a current diffusion layer provided on the contact metal layer and having conductivity greater than that of the contact metal layer, and a bonding pad layer provided on the current diffusion layer, and a mixed positive electrode-metal layer including a metal that forms the contact metal layer is present in a positive electrode side surface of the p-type semiconductor layer.

Gallium nitride-based compound semiconductor light emitting device

The present disclosure relates to a gallium nitride-based compound semiconductor light-emitting device with low driving voltage and high light emission output, which has a positive electrode comprising a transparent electrically conducting layer put into direct contact with a p-type semiconductor layer. An embodiment of the disclosure includes a gallium nitride-based compound semiconductor light-emitting device, which includes an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer, which may be formed in this order on a substrate, wherein each layer comprises a gallium nitride-based compound semiconductor, the light-emitting device has a negative electrode and a positive electrode provided on the n-type semiconductor layer and a region having a semiconductor metal concentration of 20 at. % or more, based on all metals, is present in the transparent electrically conducting film on the semiconductor side surface of the transparent electrically conducting film.

Growing community of inventors

Ichihara, Japan

Koji Kamei