International Business Machines Corporation

Renesas Electronics Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Koichi Motoyama

Chih-Chao Yang

Chanro Park

Oscar Van Der Straten

Kenneth Chun Kuen Cheng

Joseph F Maniscalco

Lawrence Alfred Clevenger

Cornelius Brown Peethala

Benjamin David Briggs

Alexander Reznicek

Christopher J Penny

Nicholas Anthony Lanzillo

Michael Rizzolo

Hsueh-Chung Chen

James John Kelly

Ruilong Xie

Kisik Choi

Hosadurga K Shobha

Somnath Ghosh

Gangadhara Raja Muthinti

Theodorus E Standaert

Praneet Adusumilli

Robert Russell Robison

Yann Mignot

Terry Allen Spooner

Shyng-Tsong Chen

Huai Huang

Kenneth C K Cheng

Scott A DeVries

Brent A Anderson

Ruqiang Bao

Su Chen Fan

Joe Lee

Gen Tsutsui

Wei Wang

Oleg Gluschenkov

Hemanth Jagannathan

Andrew Herbert Simon

Roger Allan Quon

Raghuveer Reddy Patlolla

James J Demarest

Chao-Kun Hu

Chengyu Charles Niu

Tibor Bolom

Junli Wang

Choonghyun Lee

Baozhen Li

Ekmini Anuja De Silva

Chi-Chun Liu

Seyoung Kim

Ashim Dutta

Stuart A Sieg

Dominik Metzler

Hari Prasad Amanapu

Iqbal Rashid Saraf

Jennifer Church

Frieder Heinrich Baumann

Frieder Hainrich Baumann

A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Backside power rail with tight space

A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

Semiconductor structure with backside metallization layers

A method to form a semiconductor structure for a magnetoresistive random-access memory (MRAM) device where the material for the top electrode and the bottom electrode is deposited in a single process. The method includes conformally depositing an electrode material over a magnetic tunnel junction (MTJ) pillar, under the MTJ pillar, around a spacer encapsulating and extending above the MTJ pillar. The method includes recessing the electrode material to form a thinner portion of the electrode material over the MTJ pillar. The thinner portion of the electrode material forms a thinner portion of the electrode material over the MTJ pillar that is a top electrode. The portion of the electrode material under the MTJ pillar forms a bottom electrode that is thicker than the top electrode.

Magnetoresistive random-access memory with top and bottom electrodes deposited in unison

A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Locally widened profile for nanoscale wiring structure

A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

MRAM integration with self-aligned direct back side contact

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a bottom electrode layer surrounded by a bottom dielectric layer; forming an etch-stop layer on top of the bottom electrode layer and the bottom dielectric layer; creating an opening in the etch-stop layer to expose a top surface of the bottom electrode layer; forming a first ferromagnetic layer on top of the bottom electrode layer and the etch-stop layer, with a portion of the first ferromagnetic layer filling the opening in the etch-stop layer; forming a tunnel barrier layer and a second ferromagnetic layer on top of the first ferromagnetic layer; patterning the second ferromagnetic layer, the tunnel barrier layer, and the first ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. A structure formed thereby is also provided.

MRAM structure with a T-shaped ferromagnetic layer

A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Top via interconnect with airgap

The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Dual-damascene fav interconnects with dielectric plug

A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.

MRAM device with octagon profile

A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Magneto-resistive random access memory with hemispherical top electrode

A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Metal hard mask for precise tuning of mandrels

Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Top via containing random-access memory cross-bar array

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

Damascene MRAM device

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

MRAM top electrode structure with liner layer

A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Metal-insulator-metal capacitor structure with enlarged capacitor area

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Clifton Park, NY, United States of America

Koichi Motoyama