International Business Machines Corporation

Renesas Electronics Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Koichi Motoyama

Chih-Chao Yang

Chanro Park

Oscar Van Der Straten

Kenneth Chun Kuen Cheng

Joseph F Maniscalco

Lawrence Alfred Clevenger

Cornelius Brown Peethala

Benjamin David Briggs

Alexander Reznicek

Christopher J Penny

Nicholas Anthony Lanzillo

Michael Rizzolo

Hsueh-Chung Chen

James John Kelly

Hosadurga K Shobha

Kisik Choi

Somnath Ghosh

Gangadhara Raja Muthinti

Theodorus E Standaert

Praneet Adusumilli

Robert Russell Robison

Yann Mignot

Terry Allen Spooner

Shyng-Tsong Chen

Huai Huang

Kenneth C K Cheng

Ruilong Xie

Ruqiang Bao

Su Chen Fan

Joe Lee

Gen Tsutsui

Wei Wang

Scott A DeVries

Brent A Anderson

Hemanth Jagannathan

Andrew Herbert Simon

Roger Allan Quon

Raghuveer Reddy Patlolla

James J Demarest

Chao-Kun Hu

Chengyu Charles Niu

Tibor Bolom

Junli Wang

Choonghyun Lee

Oleg Gluschenkov

Baozhen Li

Ekmini Anuja De Silva

Chi-Chun Liu

Seyoung Kim

Ashim Dutta

Stuart A Sieg

Dominik Metzler

Hari Prasad Amanapu

Iqbal Rashid Saraf

Jennifer Church

Frieder Heinrich Baumann

Frieder Hainrich Baumann

A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Top via interconnect with airgap

The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Dual-damascene fav interconnects with dielectric plug

A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.

MRAM device with octagon profile

A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Magneto-resistive random access memory with hemispherical top electrode

A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Metal hard mask for precise tuning of mandrels

Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Top via containing random-access memory cross-bar array

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

Damascene MRAM device

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

MRAM top electrode structure with liner layer

A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Metal-insulator-metal capacitor structure with enlarged capacitor area

An MRAM device is provided. The MRAM device includes a first electrode, an MRAM stack formed on the first electrode, a hardmask structure formed on the MRAM stack, and a second electrode formed on the hardmask structure. A width of an upper portion of the hardmask structure is less than a width of the MRAM stack.

Conical magnetic random access memory pillar structures

Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a magnetic tunnel junction (MTJ) stack; forming a first dielectric layer to a level above a tunnel barrier layer of the MTJ stack, the first dielectric layer partially covering the MTJ stack with a top surface of the MTJ stack being exposed; depositing an etch-stop layer covering the top surface of the MTJ stack and a top surface of the first dielectric layer; depositing a second dielectric layer covering the etch-stop layer; forming an opening in the second dielectric layer; removing a portion of the etch-stop layer above the top surface of the MTJ stack; and forming a top contact by depositing a conductive material in the opening. An MRAM structure formed thereby is also provided.

MRAM device structure

Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.

Stacked FET contact formation

A copper interconnect with self-aligned hourglass-shaped metal cap comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a metal cap formed on top of each interconnect line of the plurality of interconnect lines, where the metal cap is formed with self-aligning concave sides extending from a top surface of the dielectric layer to a top surface of the metal cap.

Copper interconnects with self-aligned hourglass-shaped metal cap

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

Etching of magnetic tunnel junction (MTJ) stack for magnetoresistive random-access memory (MRAM)

A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.

MRAM structure with multilayer encapsulation

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Clifton Park, NY, United States of America

Koichi Motoyama