Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technoloiges Austria Ag

Tinfineon Technologies Austria Ag

Klaus Schiess

Ralf Otremba

Xaver Schloegel

Josef Hoeglauer

Juergen Schredl

Oliver Haeberlen

Teck Sim Lee

Joachim Mahler

Chooi Mei Chong

Khalil Hosseini

Matteo-Alessandro Kutschak

Henrik Ewe

Josef Höglauer

Alexander Koenigsberger

Michael Treu

Markus Dinkel

Stefan Landau

Uwe Kirchner

Jürgen Schredl

Xaver Schlögel

Edward Fuergut

Gerhard Prechtl

Manfred Mengel

Rainald Sander

Oliver Häberlen

Dominic Maier

Stefan Kramp

Lee Shuang Wang

Chee Voon Tan

Tien Lai Tan

Robert Bergmann

Bernd Roemer

Guenther Lohmann

Ulrich Froehler

Anton Mauder

Thorsten Meyer

Eung San Cho

Alexander Heinrich

Uwe Wahl

Gilberto Curatola

Christian Fachmann

Thilo Stolze

Swee Kah Lee

Thomas Kilger

Peter Kanschat

Chee Yang Ng

Matthias Strassburg

Reimund Engl

Kok Yau Chua

Bernd Stadler

Chii Shang Hong

Ulrich Wachter

Bernd Schmoelzer

Fabio Brucchi

Sanjay Kumar Murugan

Soon Lock Goh

Franz Stueckler

Chan Lam Cha

Chee Hong Lee

Amirul Afiq Hud

Wee Boon Tay

Mohd Hasrul Zulkifli

Wei Han Koo

Andreas Schlögl

Guan Choon Matthew Nelson Tee

Thomas Beer

Veronika Huber

Alvin Wee Beng Tatt

Boris Plikat

Charlie Tan Tien Lai

Daniel Hoelzl

Raynold Talavera Corocotchia

Milad Mostofizadeh

Edward Andrew Jones

A semiconductor package includes: a leadframe having first, second and third die pads and leads, each die pad having upper and lower surfaces; first and second power semiconductor devices; a control semiconductor device; and a mold compound. The upper surface of each die pad is arranged within the mold compound. The lower surface of the second die pad is spaced apart from a side face of the semiconductor package by a distance that is greater than a length of the individual leads. The first power semiconductor device is mounted on the upper surface of the first die pad and electrically coupled to the second die pad by one or more first connectors extending between the first device and the upper surface of the second die pad. The upper surface of the second die pad is occupied by the one or more connectors or in direct contact with the mold compound.

Semiconductor package and method of manufacturing a semiconductor package

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

Semiconductor device including a bidirectional switch

A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

Semiconductor package, semiconductor assembly and method for fabricating a semiconductor package

A semiconductor device forming a bidirectional switch includes first and second carriers, first and second semiconductor chips arranged on the first and second carriers, respectively, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor chips. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.

Semiconductor package having a laser-activatable mold compound

A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

Semiconductor device with bond pad extensions formed on molded appendage

A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.

Method of producing an SMD package with top side cooling

A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

Device including a semiconductor chip monolithically integrated with a driver circuit in a semiconductor material

A power semiconductor arrangement includes a carrier and packages. Each package: encloses a power semiconductor die having first and second load terminals and configured to conduct a die load current between the load terminals; has a package body with a top side, a footprint side and sidewalls extending from the footprint side to the top side; a lead frame structure configured to electrically and mechanically couple the package to the carrier with the package footprint side facing the carrier, the lead frame structure including at least one first outside terminal electrically connected with the first load terminal of the die; a top layer arranged at the package top side and electrically connected with the second load terminal of the die. A top heatsink is attached to each package top layer, electrically contacted to each package top layer, and configured to conduct at least a sum of the die load currents.

Multi-package top-side-cooling

A device includes a leadframe having a diepad and leads, a compound semiconductor chip arranged over a first surface of the diepad and including gate, source electrode and drain electrodes, and an encapsulation material covering the compound semiconductor chip and diepad. A second surface of the diepad opposite the first surface is exposed from the encapsulation material. The device also includes a first lead of the leadframe electrically coupled to the gate electrode, a second lead of the leadframe electrically coupled to the source electrode, a third lead of the leadframe electrically coupled to the source electrode, and a fourth lead of the leadframe electrically coupled to the drain electrode. The third lead is configured to provide a sensing signal representing an electrical potential of the source electrode to a gate driver circuit. The gate driver circuit is configured to drive the gate electrode based on the sensing signal.

Device including a compound semiconductor chip

A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.

SMD package with flat contacts to prevent bottleneck

A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; a top layer arranged at the package top side and electrically connected with the second load terminal; and a heat spreader arranged external of the package body and in electrical contact with the top layer. A top surface of the heat spreader has an area greater than the area of the bottom surface.

SMD package with top side cooling

A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Method of manufacturing a semiconductor device

In an embodiment, an electronic component includes a high-voltage depletion mode transistor including a current path coupled in series with a current path of a low-voltage enhancement mode transistor, a diode including an anode and a cathode, and a die pad. A rear surface of the high-voltage depletion mode transistor is mounted on and electrically coupled to the die pad. A first current electrode of the low-voltage enhancement mode transistor is mounted on and electrically coupled to the die pad. The anode of the diode is coupled to a control electrode of the high-voltage depletion mode transistor, and the cathode of the diode is mounted on the die pad.

Electronic component

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Allensbach, Germany

Klaus Schiess