Globalfoundries Inc.

Advanced Micro Devices Corporation

Klaus Hempel

Sven Beyer

Markus Lenski

Andy C Wei

Stephan Kruegel

Robert Binder

Joachim Metzger

Vivien Schroeder

Thilo Scheiper

Ralf Van Bentum

Berthold Reimer

Patrick Press

Johannes F Groschopf

Ekkehard Pruefer

Roland Stejskal

Chi Dong Nguyen

Stefanie Steiner

Jan Hoentschel

Uwe Griebenow

Rolf Stephan

Richard Carter

Andreas Kurz

Martin Mazur

Andreas Ott

Elke Erben

Dina Triyoso

Dina H Triyoso

Christopher M Prindle

Chris M Prindle

A semiconductor device has an active region that includes a semiconductor layer. A transistor is formed in and above the active region, wherein the transistor has an implanted halo region that includes a halo dopant species and defines a halo dopant profile in the semiconductor layer. An implanted carbon species is positioned in the semiconductor layer, wherein the implanted carbon species defines a carbon species profile in the semiconductor layer that is substantially the same as the halo dopant profile of the implanted halo region in the semiconductor layer.

Short-channel NFET device

Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

Integrated circuits and methods of forming the same with effective dummy gate cap removal

A method of forming a semiconductor device is provided including co-implanting a halo species and carbon in a semiconductor layer with a finite tilt angle with respect to a direction perpendicular to the surface of the semiconductor layer. Furthermore, a semiconductor device is provided including an N-channel transistor comprising a halo region made of a halo species with a dopant profile formed in a semiconductor layer and a carbon species implanted in the semiconductor layer with substantially the same dopant profile as the dopant profile of the halo region.

Short-channel nFET device

When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer.

High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology

In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Method for making high-K metal gate electrode structures by separate removal of placeholder materials

When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.

High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology

By modifying the dielectric liner for a spacer structure so as to exhibit an enhanced diffusion blocking characteristic, for instance by incorporating nitrogen, the out-diffusion of P-dopants, such as boron, into the dielectric material may be significantly reduced. Consequently, transistor performance, especially of P-type transistors, may be significantly enhanced while nevertheless a high degree of compatibility with conventional techniques may be maintained.

Drain/source extension structure of a field effect transistor with reduced boron diffusion

Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

Dry etch polysilicon removal for replacement gates

Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (V) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

Metal gate stack formation for replacement gate technology

In a replacement gate approach in sophisticated semiconductor devices, the placeholder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack.

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.

Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer

Methods are provided for fabricating integrated circuits having controlled threshold voltages. In accordance with one embodiment a method includes forming a gate dielectric overlying an N-doped silicon substrate and depositing a layer of titanium nitride and a layer of tantalum nitride overlying the gate dielectric. A sub-monolayer of tantalum oxide is deposited overlying the layer of tantalum nitride by a process of atomic layer deposition, and oxygen is diffused from the tantalum oxide through the tantalum nitride and titanium nitride.

Methods for fabricating integrated circuits with controlled P-channel threshold voltage

During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Growing community of inventors

Dresden, Germany

Klaus Hempel