International Business Machines Corporation

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Klaus D Beyer

Louis L Hsu

Victor J Silvestri

Chang-Ming Hsieh

Andrie S Yapsir

Dominic Joseph Schepis

Patrick Ronald Varekamp

Fen Fen Jamin

Taqi Nasser Buti

Stephen Edward Greco

David Edward Kotecki

Jacob Riseman

John M Aitken

Tsorng-Dih Yuan

Billy L Crowder

Eric Mendel

Effendi Leobandung

Kevin K Chan

Kern Rim

Seiki Ogura

Subramanian Srikanteswara Iyer

Steven John Koester

James Douglas Warnock

Michael John Hargrove

Nivo Rovedo

Karen A Nummy

Christopher Carr Parks

Mark A Jaso

Atul Champaklal Ajmera

Joseph S Logan

William L Guthrie

Scott R Stiffler

Michael R Poponiak

Gobinda Das

San-Mei Ku

Edward C Fredericks

Peter I Smeys

William J Patrick

Patricia A O'Neil

William A Pliskin

Paul M Schaible

Charles L Standley

Stanley R Makarewicz

James S Makris

Kathleen A Perry

Tsu-Hsing Yeh

Subodh K Kulkarni

Tsoring-Dih Yuan

Robert H Kastl

Deborah A Ryan

A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Shallow trench isolation structure for strained Si on SiGe

In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

Triple oxide fill for trench isolation

An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH and O and adding a controlled amount of NH to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O to NH in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Method of formation of an oxynitride shallow trench isolation

Oxynitride shallow trench isolation and method of formation

A method for forming an isolation trench in a silicon or silicon-on-insulator substrate is described in which a trench is formed in the semiconductor structure (containing a multiple layer structure of Si, SiO , and SiN layers) and an undoped polysilicon layer is deposited on the bottom and sidewalls of the trench and on the surface of the region adjacent to the trench. A substantial portion of the trench is left unfilled by the undoped polysilicon layer deposited. The polysilicon layer is thermally oxidized to form a thermal oxide that fills the trench and thereby avoids forming a birds-beak formation of the thermal oxide above the sidewalls of the trench. The isolation structure may be planarized by either removing the polysilicon layer from the region adjacent to the trench before oxidation or later removing the oxide from the SiN layer and adjusting height of the oxide in the trench. Alternatively, either a doped polysilicon layer or a doped SiO layer may be formed above the silicon nitride layer before the undoped polysilicon layer is deposited. In this case, the isolation structure is heat treated prior to oxidization to drive dopants from the doped layer into the undoped polysilicon layer, thereby forming a secondarily doped polysilicon layer from the undoped polysilicon layer. The doped layers are then removed by selective wet etching and expose the silicon nitride layer prior to oxidation.

Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon

A method is disclosed for forming shallow trench isolation (STI) on a thin silicon-on-insulator (SOI) substrate. The method comprises depositing a first polysilicon layer; depositing a polish stop layer on the first polysilicon layer; forming a plurality of trenches in the substrate; filling the trenches with silicon oxide; CMP polishing a first portion of the silicon oxide layer down to the polish stop layer; etching a second portion of the silicon oxide layer down to below the polish stop layer and above the first polysilicon layer; removing the polish stop layer; depositing a second polysilicon layer; and forming a polysilicon gate comprised of the first and second polysilicon layers. Well ion implants may be performed prior to gate formation, thereby preventing exposure of STI oxide to sacrificial oxide growth and removal, eliminating excessive recess in STI structures. STI oxide seam leakage due to polysilicon sidewalls remaining after polysilicon gate etch are also avoided.

Method of forming shallow trench isolation for thin silicon-on-insulator substrates

A planarizing method involves a first polishing step in which a relatively hard, low compressibility pad removes excess material of a first layer and planarizes the first layer. Deep defects emanating from the polishing surface formed during the first polishing step are then enlarged and filled with a second layer. After filling, and optionally annealing, the second layer is planarized by polishing with a relatively soft and high compressibility pad or by anisotropic etching.

Method for removing crevices induced by chemical-mechanical polishing

SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

SOI transistor having a self-aligned body contact

An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

Large scale IC personalization method employing air dielectric structure

Larce scale IC personalization method employing air dielectric structure

Method of forming a SOI transistor having a self-aligned body contact

A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

Reach-through isolation silicon-on-insulator device

A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

Bonded wafer structure having a buried insulation layer

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Poughkeepsie, NY, United States of America

Klaus D Beyer