International Business Machines Corporation

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Other

Siemens Aktiengesell Schaft

Klaus B Roithner

Karl Paul Muller

Bernhard Poschenrieder

Richard L Kleinhenz

Masakatsu Tuschiaki

Toru Watanabe

The present invention is an apparatus for distributing reactant gases across the substrate mounted in a reaction chamber. The apparatus is capable of being utilized in both vapor deposition and etching processes. The apparatus substantially compensates for the problem of non-uniformity of vapor deposition and etching at the edges of the wafers caused by gas depletion. A gas distribution plate having a plurality of apertures extending therethrough is attached to an interior surface of the reaction chamber. At least one vacuum sealed partition is disposed between a surface of the gas distribution plate and the interior surface of the chamber. The partition separates the space between the plate and reaction chamber into gas distribution zones. A gas inlet is connected to each gas distribution zone. Each gas inlet line has at least one mass flow controller which regulates the flow of gas to each gas distribution zone. The mass flow controllers are utilized to ensure a uniform rate of chemical vapor deposition or etching across the surface of the substrate.

Distribution plate for a reaction chamber with multiple gas inlets and separate mass flow control loops

A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.

Pad stack with a poly SI etch stop for TEOS mask removal with RIE

In a method of etch profile shaping through wafer temperature control during an etch process wherein deposition of a passivation film is temperature dependent, a gap between a semiconductor wafer to be etched and a cathode is pressurized at a first pressure, and the pressure in the gap is changed to a second pressure at a predetermined time during the etch process, thereby altering heat transfer from the semiconductor wafer to the cathode. The temperature of the wafer is adjusted one or more times during an etching process to control profile shaping of deep trenches, contact holes and shapes for mask opening shaping during the etch process.

Etch profile shaping through wafer temperature control

A capacitance storage trench for a DRAM cell includes a trench having at least one sidewall, a bottom wall and a plurality of rods extending away from the bottom wall. The at least one sidewall, the bottom wall and the rods are coated with a capacitive dielectric layer. A layer of semiconductive material is disposed over the dielectric layer. The plurality of rods expand the overall surface area of the trench and thus, provide a significant increase in capacitance storage of the storage trench. The capacitance storage trench is formed in a method which includes the steps of forming a plurality of buried oxygen precipitates in a selected region of a substrate and using the oxygen precipitates as micromasks during a conventional trench etch process.

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Wappingers Falls, NY, United States of America

Klaus B Roithner