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Matsushita Electric Industrial Co., Ltd.

Matsushita Electric Ind. Co., Ltd.

Kiyoshi Uchiyama

Carlos Alberto Paz De Araujo

Narayan Solayappan

Yasuhiro Shimada

Koji Arita

Keisuke Tanaka

Larry D McMillan

Shinichiro Hayashi

Jolanta Bozena Celinska

Vikram Joshi

Tatsuo Otsuki

A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.

Semiconductor memory device

A ferroelectric memory ( ) includes a plurality of memory cells ( ) each containing a ferroelectric thin film ( ) including a microscopically composite material having a ferroelectric component ( ) and a dielectric component ( ), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400&deg; C. and 550&deg; C.

Ferroelectric composite material, method of making same and memory utilizing same

A method of forming a Bi-layered superlattice material on a substrate using chemical vapor deposition of a precursor solution of trimethylbismuth and a metal compound dissolved in an organic solvent. The precursor solution is heated and vaporized prior to deposition of the precursor solution on an integrated circuit substrate by chemical vapor deposition. No heating steps including a temperature of 650&deg; C. or higher are used.

Chemical vapor deposition method of making layered superlattice materials using trimethylbismuth

A ferroelectric integrated circuit including a substrate supporting a thin film ferroelectric material and an electrode layer in contact with the ferroelectric material, the ferroelectric material comprising a compound including a metal element, the electrode comprising the metal element. The metal element of the ferroelectric material may exist in the electrode in the pure metal form, as an alloy, as part of a crystalline compound, or as part of an amorphous material. The electrodes may be formed by a single layer, or as multi-layer structures, providing the layer adjacent the ferroelectric contains at least one of the metal elements of the ferroelectric. The electrode is formed at the eutectic temperature of its constants.

Electrodes for ferroelectric components

A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (&ldquo;RTP&rdquo;) and furnace annealing steps.

Chemical vapor deposition process for fabricating layered superlattice materials

A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.

Method of making ferroelectric material utilizing anneal in an electrical field

A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (&ldquo;RPA&rdquo;) technique with a ramp rate of 30&deg; C./second at a hold temperature of 650&deg; C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.

Rapid-temperature pulsing anneal method at low temperature for fabricating layered superlattice materials and making electronic devices including same

An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.

Integrated circuit device including a layered superlattice material with an interface buffer layer

Data is read out from a ferroelectric film with its remnant polarization associated with one of two possible logical states of the data and with a bias voltage applied to a control gate electrode over the ferroelectric film. The ferroelectric film creates either up or down remnant polarization. So the down remnant polarization may represent data &ldquo;1&rdquo; while the up or almost zero remnant polarization may represent data &ldquo;0&rdquo;, for example. By regarding the almost zero remnant polarization state as representing data &ldquo;0&rdquo;, a read current value becomes substantially constant in the data &ldquo;0&rdquo; state. As a result, the read accuracy improves. Also, if imprinting of one particular logical state (e.g., data &ldquo;1&rdquo;) is induced in advance, then the read accuracy further improves.

Semiconductor memory device, method for driving the same and method for fabricating the same

Source/drain regions for a field effect transistor are defined in a semiconductor substrate with a channel region interposed therebetween. A first gate electrode is formed over the semiconductor substrate with an insulating film sandwiched therebetween and has a gate length shorter than the length of the channel region. A ferroelectric film is formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film. A second gate electrode is formed to cover the ferroelectric film.

Semiconductor memory and method of driving semiconductor memory

A tunneling transistor is provided as an effective means for miniaturization of a semiconductor integrated circuit having nonvolatile memory. An insulating layer is disposed on a silicon substrate. A source and a drain are disposed on the insulating layer, with an insulator of a few nanometers in thickness that provides a tunnel barrier being interposed between the source and the drain. A ferroelectric layer that exhibits spontaneous polarization is disposed directly above a region of the source that is adjacent to the insulator. With this construction, when the ferroelectric layer is polarized in a predetermined direction, at least a portion of the region of the source adjacent to the insulator forms a depletion region, with it being possible to vary the amount of current tunneling through the insulator depending on whether the ferroelectric layer is polarized or not.

Tunneling transistor applicable to nonvolatile memory

A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (&ldquo;RRA&rdquo;) technique with a ramping rate of 50&deg; C./second at a hold temperature of 650&deg; C. for a holding time of 30 minutes.

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Colorado Springs, CO, United States of America

Kiyoshi Uchiyama