Shinko Electric Industries Co., Ltd.

Kiyoshi Oi

Noriyoshi Shimizu

Takashi Kurihara

Yasuyoshi Horikawa

Tomoo Yamasaki

Akihiko Tateiwa

Kei Murayama

Naoyuki Koizumi

Mitsuhiro Aizawa

Teruaki Chino

Akihito Takano

Masahiro Sunohara

Yoshihiro Machida

Hidehiko Kira

Akio Rokugawa

Yuichi Taguchi

Tomoharu Fujii

Takashi Kubota

Kiyoaki Iida

Takatoyo Yamakami

Fumimasa Katagiri

Yuichiro Shimizu

Shota Miki

Tomotake Minemura

Yukinori Hatori

Toru Hizume

Yohei Igarashi

Satoshi Otake

Hiroyuki Saito

Koyuki Kawakami

Amane Kaneko

An embedded PCB includes a first substrate, an electronic component mounted on the first substrate, a second substrate provided on a side opposite to the first substrate with the electronic component interposed therebetween, and electrically connected to the first substrate via substrate bonding members, and an encapsulating resin filled between the first and second substrates, covering the electronic component, and also filled between the electronic component and the first substrate. The first substrate includes, on a side closer to the electronic component, pads to be bonded to electrodes of the electronic component via bonding portions, and a protective insulating layer including openings. The pads include outermost peripheral pads in an outermost periphery including four corners of an approximately rectangular area in a plan view, and inner pads in an area surrounded by the outermost peripheral pads.

Embedded printed circuit board

A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin formed from a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the encapsulation resin. The covering resin is disposed on the upper surface of the upper substrate and covers a side surface of the wiring layer.

Semiconductor device

A composite wiring substrate includes a first wiring substrate including a first connection terminal, a second wiring substrate including a second connection terminal facing the first connection terminal, and a joint material joining the first connection terminal and the second connection terminal. The first outline of the first connection terminal is inside the second outline of the second connection terminal in a plan view. The joint material includes a first portion formed of an intermetallic alloy of copper and tin, and contacting each of the first connection terminal and the second connection terminal, and a second portion formed of an alloy of tin and bismuth, and including a portion between the first outline and the second outline in the plan view. The second portion contains the bismuth at a higher concentration than in the eutectic composition of a tin-bismuth alloy, and is separated from the second connection terminal.

Composite wiring substrate and semiconductor device

A wiring substrate includes a first connection terminal and a protective insulation layer. The first connection terminal is electrically connected to a wiring layer by a via wiring and projects upward from an upper surface of an insulation layer. The protective insulation layer is located on the upper surface of the insulation layer to contact and cover a portion of a side surface of the first connection terminal. The first connection terminal includes a lower portion that is continuous with the via wiring and an upper portion that is continuous with the lower portion. The lower portion is smaller in crystal grain size than the upper portion. The lower portion and the upper portion are formed from the same metal material. The side surface of the lower portion has a higher roughness degree than the side surface of the upper portion.

Wiring substrate and semiconductor device

A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.

Wiring substrate, semiconductor device, and method for manufacturing wiring substrate

A wiring substrate includes a first multi-layer wiring layer having a stacked via structure including a first electrode pad, a second multi-layer wiring layer having a non-stacked via structure including a second electrode pad. The second electrode pad is formed on an uppermost first insulating layer. The first electrode pad is formed on a second insulating layer which is located to a position lower by one layer than the first insulating layer, and the first electrode pad is arranged in an opening portion of the first insulating layer such that the upper face and the side face of the first electrode pad are exposed.

Wiring substrate, semiconductor device, method of manufacturing wiring substrate, and method of manufacturing semiconductor device

A semiconductor device includes a wiring substrate including a first electrode in which a cross-sectional shape is an inverted trapezoidal shape, a semiconductor chip including a second electrode in which a cross-sectional shape is an inverted trapezoidal shape, a metal bonding material bonding a tip end of the first electrode and a tip end of the second electrode which face each other, and an underfill resin filled between the wiring substrate and the semiconductor chip, the underfill resin covering a side face of each of the first electrode and the second electrode and a side face of the metal bonding material.

Semiconductor device and method of manufacturing the same

A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring layer having a wiring pitch narrower than the wiring pitch of the first multi-layer wiring layer. The external connection pads are exposed from the insulating layer of the second multi-layer wiring layer.

A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film.

Method of manufacturing semiconductor device

A bonding tool holds a lower chip against a release tape held by a suction force. The bonding tool has an electronic-component suction opening against which the lower chip is held and, surrounding the electronic-component suction opening, a trench that accommodates the release tape. The lower chip is heated, by being pressed against an underfill material and, thus, an area on which an upper chip is mounted is formed in such a manner that the underfill material protrudes out from the lower chip. During the heating, because an expanded part of the release tape, expanded due to heat, is inserted into the trench, no folded line is formed on the upper surface of the underfill material.

Electronic packaging apparatus and electronic packaging method

A semiconductor device includes: a wiring board which includes a first face and a second face and in which a conductor pattern and a through part are provided; an electronic component which includes an electrode pad forming face where an electrode pad is formed and which is housed in the through part so that the electrode pad forming face is provided on the first face side; a seal resin which is provided in the through part and the electrode pad forming face, seals the electronic component and includes a first plane exposing a connection face of the electrode pad; and a wiring pattern which is provided in the first face of the wiring board and the first plane of the seal resin and electrically connects the connection face of the electrode pad with a first connected face of the conductor pattern, and which includes a pad part.

Semiconductor device having electronic component in through part, electronic device, and manufacturing method of semiconductor

A wiring board adapted for mounting an electronic component has the form of a structure in which a plurality of wiring layers are stacked one on top of another with an insulating layer interposed therebetween and are interconnected through via holes formed in the insulating layers, respectively. A plurality of openings are formed through the structure in a region where a wiring is not formed, extending through the structure in a thickness direction thereof. Further, solder resist layers are formed on the outermost wiring layers, respectively, and exposing pad portions defined in desired locations in the outermost wiring layers.

Wiring board and electronic component device

A manufacturing method of a semiconductor device includes a film state underfill resin adhering step wherein film state underfill resin in a semi-cured state is adhered on the first surface of the board main body without forming a gap between the first surface of the board main body and the pad; a flattening step wherein an upper surface of the film state underfill resin is flattened; a chip connecting step wherein the semiconductor chip is pressed onto the upper surface of the film state underfill resin after the flattening step so that the semiconductor chip is flip chip connected to the pad; and an underfill resin forming step wherein the film state underfill resin is cured so that the underfill resin is formed between the semiconductor chip and the wiring board.

Manufacturing method of semiconductor device having underfill resin formed without void between semiconductor chip and wiring board

A module substrate is provided. The module substrate includes: a core portion; a build-up layer formed on the core portion and including a wiring pattern and an insulating layer; an optical transmission mechanism including: an optical transmission component including an optical waveguide, and a mounting portion on which a semiconductor element is to be mounted. The mounting portion is electrically connected to the optical transmission mechanism via the wiring pattern. The mounting portion includes a first mounting portion and a second mounting portion, and the optical transmission mechanism is disposed between the first mounting portion and the second mounting portion.

Module substrate including optical transmission mechanism and method of producing the same

A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.

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Nagano, Japan

Kiyoshi Oi