Texas Instruments Corporation

Sony Corporation

Sony Electronics Inc

Other

Kiyoshi Mori

Shailesh R Kadakia

A vertical floating gate transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a floating gate electrode in a trench that extends vertically through those regions and a control or programming gate electrode above and separated from the floating gate electrode. A process for forming the vertical floating gate transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and the floating and control gates. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.

Vertical floating gate transistor with epitaxial channel

A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench that extends vertically through those regions. A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.

Epitaxial channel vertical MOS transistor

A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench hat extends vertically through those regions. A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region. Then, the upper source/drain region is implanted above the lower source/drain A region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate. Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry. Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield. Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity.

A method of localized control of integrated circuit parameters according to the present invention is used to adjust a the threshold voltage of an integrated circuit by irradiating an inoperable area with a focused ion beam such that the determination of the correct threshold voltage is facilitated without having to refabricate the integrated circuit in its entirety.

Localized control of integrated circuit parameters using focus ion beam

A method for identifying those process steps which produce 'high risk' particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.

Identifying causes of semiconductor production yield loss

Prioritizing efforts to improve semiconductor production yield

A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked --a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

Vertical memory cell array and method of fabrication

A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode. Series drain resistance, and gate-to-drain capacitance, is minimized by a deeper implant of the drain region away from the trench and under the electrical interconnection to the drain diffusion.

Method of making a vertical MOS transistor

An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

Vertical floating-gate transistor

An MOS transistor having a vertical channel disposed along the sides of a trench is disclosed. The transistor is formed in an epitaxial layer on a substrate, with the channel region formed within the epitaxial layer by way of ion implantation and diffusion; the ion implantation is done in such a manner that the epitaxial layer is divided into a portion above the channel region (source region) and a portion below the channel region (drain region). A trench is etched to extend through the epitaxial region into the substrate, gate oxide is grown along the sides of the trench, and a polysilicon gate electrode is deposited adjacent the gate oxide along the walls of the trench. The epitaxial layer allows the drain and source regions of the transistor to have substantially equal carrier concentrations, said concentrations being relatively low. As a result, the transistor operates the same regardless of whether the upper portion of the epitaxial layer serves as the drain or as the source, for digital logic applications. In addition, the relatively light doping of the source and drain regions provides for a high diode breakdown voltage, and prevents punch-through of the channel region at high bias voltages.

Symmetric vertical MOS transistor with improved high voltage operation

A two-transistor programmable memory cell (FIG. 1A, 20) with one vertical floating gate transistor (VT) and one planar transistor (PT)--the planar transistor can be optimized for programming with low current (longer channel length and narrower channel width), while the vertical transistor can be optimized for reading with high current (shorter channel length and wider channel width). The vertical transistor is formed in a trench (22) with a source region (15) and a sub-source VT drain region (23). The planar transistor includes the source region (15) and a co-planar PT drain region (27).

Two-transistor programmable memory cell with a vertical floating gate

Vertical MOS transistor

An electrically erasable, progammable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

A method and structure for adjustment of the threshold voltage of a vertical metal-oxide-semiconductor transistor. Chemical vapor deposition of doped silicon dioxide and annealing are used to form a voltage-threshold-adjustment region in at least the channel layer of the transistor adjacent to the trench wall.

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San Antonio, TX, United States of America

Kiyoshi Mori