Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Vlsi Engineering Corp.

Elpida Memory, Inc.

Renesas Electronics Corporation

Hitachi Microcomputer Engineering, Ltd.

Hitachi Device Engineering Co., Ltd.

Other

Hitachi Ulsi Engineering Corp.

Ps4 Luxco S.a.r.l.

Commissariat a L'energie Atomique Et Aux Energies

Vlsi Engineering Corporation

Hitachi, Ltd., Hitachi Vlsi Engineering Corporation

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Kiyoo Itoh

Takeshi Sakata

Masashi Horiguchi

Ryoichi Hori

Masakazu Aoki

Takayuki Kawahara

Yoshiki Kawajiri

Takao Watanabe

Goro Kitsukawa

Jun Etoh

Hitoshi Tanaka

Yoshinobu Nakagome

Katsutaka Kimura

Tomonori Sekiguchi

Hideyuki Matsuoka

Kunio Uchiyama

Koichiro Ishibashi

Kazuo Nakazato

Riichiro Takemura

Katsuhiro Shimohigashi

Kazuhiko Kajigaya

Hiroyuki Mizuno

Hiromasa Noda

Noriyuki Homma

Osamu Nagashima

Toshikazu Shimada

Youji Idei

Hiroshi Mizuta

Motoyasu Terao

Yutaka Kobayashi

Satoru Hanzawa

Toshiaki Yamanaka

Takahide Ikeda

Hideaki Uchida

Shinji Nakazato

Masahiro Yamamura

Nobuo Tanba

Hideo Sunami

Yoshikazu Saito

Eiji Kume

Shin'ichi Ikenaga

Kenichi Osada

Shinichiro Kimura

Takesada Akiba

Ryoichi Kurihara

Takaaki Noda

Norio Miyake

Masanao Yamaoka

Toshiyuki Mine

Yusuke Kanno

Masaharu Kubo

Shigeru Nishimatsu

Ken Yamaguchi

Norikazu Hashimoto

Shin'ichiro Kimura

Tatsuya Teshima

Kenchi Ito

Yasushi Watanabe

Akira Kotabe

Ryuta Tsuchiya

Hisayuki Higuchi

Makoto Suzuki

Shinichi Takayama

Masanori Isoda

Toshihiko Sato

Shinichi Ikenaga

Haroon Ahmed

Tatsumi Uchigiri

Eiji Yamasaki

Goro Kitukawa

Kazumasa Yanagisawa

Masayuki Miyazaki

Katsuro Watanabe

Kazuyoshi Oshima

Hideo Nakamura

Tomoyuki Ishii

Norikatsu Takaura

Osamu Nishii

Toshiaki Masuhara

Osamu Minato

Yoshifumi Kawamoto

Kenzo Kurotsuchi

Katsuro Sasaki

Eiji Takeda

Kunihiko Yamaguchi

Kazuhiko Sagara

Kan Takeuchi

Manabu Tsunozaki

Hirotoshi Tanaka

Sigeo Ihara

Tetsu Udagawa

Takashi Ishigaki

Suguru Tachibana

Junko Tanaka

Kyoko Ishii

Noriyuki Honma

Toru Toyabe

Amara Amara

Yasushi Gotoh

Shin&prime;ichiro Kimura

A static random access memory (SRAM) comprises a plurality of memory cells each having a pair of cross-coupled inverters, a first of the inverters being supplied by first and second power supply rails and a second of the inverters being supplied by third and fourth supply rails, an input of the second inverter being coupled to a first bit line via a first transistor; and a power supply circuit adapted to apply a first voltage difference across the first and second power supply rails and a second voltage difference across the third and fourth power supply rails, the second voltage difference being greater than the first voltage difference.

Static random access memory

A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.

Semiconductor device

The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.

Semiconductor recording device

A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.

CMOS circuit and semiconductor device

To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.

Semiconductor storage device

A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Static memory cell having independent data holding voltage

There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.

CMOS circuit and semiconductor device with multiple operation mode biasing

A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.

Semiconductor integrated circuits with power reduction mechanism

A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.

In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.

Voltage supply with low power and leakage current

The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Semiconductor integrated circuit device having power reduction mechanism

Growing community of inventors

Higashikurume, Japan

Kiyoo Itoh