Cavium, Inc.

Kishore Badari Atreya

Ajeer Salil Pudiyapura

Ravindran Suresh

Nimalan Siva

Harish Krishnamoorthy

Premshanth Theivendran

Mohan Balan

A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Compiler architecture for programmable application specific integrated circuit based network devices

A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.

Software assisted hardware configuration for software defined network system-on-chip

Algorithm to achieve optimal layout of instruction tables for programmable network devices

Algorithm to derive logic expression to select execution blocks for programmable network devices

Code generator for programmable network devices

Code processor to build orthogonal execution blocks for programmable network devices

A parser engine programming tool configured to receive an input file representing a directly connected cyclical graph or tree of decision points for parsing a range of incoming packet headers, automatically generate all possible paths within the graph and thereby the associated possible headers, and convert the determined paths/headers into a proper format for programming memory of a parser engine to parse the determined headers (represented by the paths).

Parser engine programming tool for programmable network devices

Algorithm to achieve optimal layout of decision logic elements for programmable network devices

A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.

Co-verification&#x2014;of hardware and software, a unified approach in verification

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San Jose, CA, United States of America

Kishore Badari Atreya