International Business Machines Corporation

Lsi Logic Corporation

Adeia Semiconductor Bonding Technologies Inc.

Cisco Technology, Inc.

Elenion Technologies, LLC

Lsi Corporation

Agere Systems Inc.

Invensas LLC

Kishor V Desai

Charles Gerard Woychik

Ravinder Kachru

Kalpendu Shastri

Soham Pathak

Belgacem Haba

Vipulkumar K Patel

Bipin Dama

Maniam B Alagaratnam

Sunil A Patel

Huailiang Wei

Chok J Chia

Qwai Hoong Low

Terrence Caskey

John Pierre McCormick

Harold Kohn

Ilyas Mohammed

Gregg J Armezzani

Sarathy Rajagopalan

Cyprian Emeka Uzoh

Craig S Mitchell

Michael J Hochberg

John William Osenbach

Chris Togami

Ari Jason Novack

Ruizhi Shi

Utpal Kumar Chakrabarti

Randall Joseph Stutzman

Robert H Katyl

Daniel Jacob Blumenthal

Amit Kumar Sarkhel

George Henry Thiel

Thomas G Macek

Nathan A Nuttall

Holger N Klein

Timothy F Carden

Stephen R Engle

Vilakkudi G Veeraraghavan

Nelson P Franchak

Tamar A Sholtes

David Henry Kinghorn

Glenn O Dearing

John J Pessarchick

Mark Andrew Webster

Prakash B Gothoskar

Ellis Chau

Mark Adam Bachman

Leah Miller

Rao Yelamarty

Jeffrey S Perkins

Maganlal S Patel

Thomas Robert Daugherty

Sang Il Lee

Kaushik Patel

Jeffery S Perkins

Wael Zohni

Benson Chan

Sanjeev Balwant Sathe

Donald P Seraphim

Edwin Lorimer Thomas

Kumar Nagarajan

John Henry Sherman

Ajit Kumar Trivedi

Zafer S Kutlu

Ramaswamy Ranganathan

Alan D Knight

John Matthew Fangman

George J Saxenmeyer, Jr

David E Engle

Fletcher W Chapin

Brian Thomas Vaccaro

Joze E Antol

Reinhold E Tomek

John G Baumberger

Paul Joseph Hart

James R Webb

William S Ebert

Joseph Hromek

Richard C Senger

James R Bentlage

Endwell

Ronald J Romanosky

Edward Vytlacil

John James Pessarchick

Roupen L Keusseyan

Kohn Harold

Craig Mitchell

Charles G Woychik

Two semiconductor chips are optically aligned to form a hybrid semiconductor device. Both chips have optical waveguides and alignment surface positioned at precisely-defined complementary vertical offsets from optical axes of the corresponding waveguides, so that the waveguides are vertically aligned when one of the chips is placed atop the other with their alignment surface abutting each other. The position of the at least one of the alignment surface in a layer stack of its chip is precisely defined by epitaxy. The chips are bonded at offset bonding pads with the alignment surfaces abutting in the absence of bonding material therebetween.

Optically aligned hybrid semiconductor device and method

An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of the first and second support portions is comprised of a semiconductor material. The first support portion includes first and second opposed major surfaces and a plurality of first conductive vias extending through the first support portion substantially perpendicular to major surfaces. The second support portion includes first and second opposed major surfaces and a plurality of second conductive vias extending through the second support portion substantially perpendicular to the first and second major surfaces of the second support. The redistribution layer can be disposed between the second surfaces of the first and second support portions. The passive device can be positioned at least partially within the redistribution layer and electrically connected with one or more of the first conductive vias and the second conductive vias.

Low CTE interposer

A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Low cost hybrid high density package

An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion ('CTE') of less than 12 parts per million per degree, Celsius ('ppm/&#xb0; C.').

An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Molded glass lid for wafer level packaging of opto-electronic assemblies

Techniques for coupling light from a waveguide array to a single mode fiber array are described. In an embodiment, lateral misalignment of an array of focusing lenses and an array of optical fiber ferrules held into alignment by a lens holder sub-assembly is compensated by tilting the lens holder sub-assembly with respect to the propagation axis of the light being coupled by the lens holder-subassembly. Since the amount of tilt can be adjusted according to the degree of lateral misalignment, lens holder sub-assemblies manufactured with varying degrees of misalignment may be utilized to couple light into single mode fiber-optic cable. In addition, the same technique can also be used to compensate for other defects as well, such as angular errors in manufacturing or placement of a turning mirror or prism used to direct light into the lens holder sub-assembly.

Coupling light from a waveguide array to single mode fiber array

An apparatus for providing single mode optical signal coupling between an opto-electronic transceiver and a single mode optical fiber array takes the form of a lens array and a ferrule component. The lens array includes a plurality of separate lens element disposed to intercept a like plurality of single mode optical output signal from the opto-electronic transceiver and provide as an output a focused version thereof. The ferrule component includes a plurality of single mode fiber stubs that are passively aligned with the lens array and support the transmission of the focused, single mode optical output signals towards the associated single mode optical fiber array.

Single mode fiber array connector for opto-electronic transceivers

A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/&#xb0; C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

Low-stress TSV design using conductive particles

An arrangement for providing passive alignment of optical components on a common substrate uses a set of reference cavities, where each optical device is positioned within a separate reference cavity. The reference cavities are formed to have a predetermined depth, with perimeters slightly larger than the footprint of their associated optical components. The reference cavity includes at least one right-angle corner that is used as a registration corner against which a right-angle corner of an associated optical component is positioned. The placement of each optical component in its own reference cavity allows for passive optical alignment to be achieved by placing each component against its predefined registration corner.

Arrangement for placement and alignment of opto-electronic components

A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.

Reduced stress TSV and interposer structures

A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a 'platform' (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

Wafer scale packaging platform for transceivers

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Fremont, CA, United States of America

Kishor V Desai