Freescale Semiconductor,inc.

Kirk J Strozewski

Yeong-Jyh Tom Lii

Kathleen C Yu

Hector Adrian Sanchez

Janos Farkas

Terry Grant Sparks

Chi-Min Yuan

Mehul D Shroff

Stanley Michael Filipiak

Kevin D Lucas

Kevin Dean Lucas

John C Flake

Yuri Solomentsev

Robert Boone

Bradley P Smith

Cindy K Goldberg

Jason T Porter

Ajay Singhal

Marc J Olivares

A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

Layout modification using multilayer-based constraints

A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Semiconductor device having a multiple thickness interconnect

A semiconductor fabrication method that includes forming a film () comprising an imaging layer () and an under layer () over a semiconductor substrate (). The imaging layer () is patterned to produce a printed feature () having a printed dimension (). The under layer () is then processed to produce a sloped sidewall void () in the under layer () wherein the void () has a finished dimension () in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer () may include exposing the wafer to high density low pressure Nplasma.

Semiconductor fabrication method for making small features

Dummy features () are formed within an interlevel dielectric layer (). Passivation layers (and) are formed by electroless deposition to protect the underlying conductive regions (and) from being penetrated from the air gaps (). In addition, the passivation layers (and) overhang the underlying conductive regions (and), thereby defining dummy features (and) adjacent the conductive regions (and). The passivation layers (and) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Method for forming a passivation layer for air gap formation

Method for forming a semiconductor interconnect with multiple thickness

A method ( ) for correcting lithography error includes generating ( ) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize ( ) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern ( ) has isolated features ( ) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern ( ) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Lithography correction method and device

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Round Rock, TX, United States of America

Kirk J Strozewski