Intel Corporation

Kinya Ichikawa

Robert L Sankman

Yoshihiro Tomita

Takashi Kumamoto

Jiro Kubota

Chia-Pin Chiu

Kenzo Ishida

Yohko Mashimoto

Shawna M Liff

Omkar G Karhade

Nitin A Deshpande

Masayuki Akiba

Johanna M Swan

Debendra Mallik

Kenji Takahashi

Eric Jin Li

Sriram Dattaguru

Terry Lee Sterrett

Shuji Inoue

Lesley A Polka Wood

Takaya Miwa

Seiichiroh Seki

Yukihiro Murakami

Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

High density substrate interconnect formed through inkjet printing

A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

Picture frame stiffeners for microelectronic packages

Method for making high density substrate interconnect using inkjet printing

A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.

Methods of connecting a first electronic package to a second electronic package

A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

In-package microelectronic apparatus, and methods of using same

In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.

Substrate connector for integrated circuit devices

A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

Stackable integrated circuit packaging

Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

Encapsulated stack of dice and support therefor

Encapsulation of a stack of semiconductor dice

Embodiments include a generally planar patch substrate having external connection pads on one side, electrical connections connected to the external connection pads and extending through the substrate, and plated contacts formed on the electrical connections and extending beyond the other side of the patch substrate. The external connection pads may be connected to one electrical device using solder bumps or balls, and the plated contacts may be connected to contacts of another electrical device by thermo-compression bonding. Also, a surface of the patch substrate having the plated contacts may be attached to the other electrical device using an electrically insulating adhesive. Moreover, the plated contacts may have a smaller surface area than the external connection pads, so that the other electrical device can also have smaller contacts, leaving more space for electrically conductive traces to the contacts on the surface and within layers of the other electrical device.

Patch substrate for external connection

In one embodiment of the invention, a die is bonded on a strip carrier frame having a carrier alignment landmark. A tape automated bonding (TAB) strip having a TAB alignment landmark is aligned with the strip carrier frame. The TAB strip is bonded to the strip carrier frame to form a bonded unit.

Device packaging using tape automated bonding (TAB) strip bonded to strip carrier frame

A method for producing a molded flip chip package is described. According to one embodiment, an incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold, and a resin is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate, and the resin is cured by maintaining the mold at an elevated temperature for a predetermined amount of time.

Molded flip chip package

A socket for mounting a processor and/or a board has a substrate with a built in socket. The socket has conductive, elastically deformable terminals. The socket may be mounted to a processor and a board without using conventional surface mount technology, instead providing a mechanical contact mechanism between the socket and the board or processor. An adhesive layer may also be used to connect the socket to a processor and/or a board.

Easy mount socket

A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, preferably epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

Growing community of inventors

Tsukuba, Japan

Kinya Ichikawa