Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Inc.

Agere Systems Guardian Corp.

Other

American Telephone & Telegraph Co., At&t Bell Laboratories

Sychip Inc.

At+t Corp.

Bell Telephone Laboratories

Avaya Technology LLC

American Telephone and Telegraph, Co.

At&t Ipm Corp.

King Lien Tai

Yinon Degani

Thomas Dixon Dudderar

Robert Charles Frye

Richard Joseph Pimpinella

Avishay Katz

Thaddeus John Gabara

Richard T Kraetsch

Chien-Hsun Lee

Dean Paul Kossives

Yee Leng Low

Ratnaji R Kola

Charley Chunlei Gao

Yiu-Man Wong

Cheng-Hsuan Chen

Leonard W Schaper

Maureen Yee Lau

Ashraf W Lotfi

Mindaugas Fernand Dautartas

Zhengxiang Ma

Yiu-Huen Wong

Alan Michael Lyons

Elsa Reichmanis

John Thomson, Jr

Hui Wu

Ron Jay Barnett

Fan Ren

Frederick Vratny

Adam Heller

Anatoly Feygenson

Joseph Henry Condon

Cletus W Wilkins, Jr

Howard Zehua Chen

Michael Gunnar Johnson

Byung Joon Han

Peter Roland Smith

John M Segelken

Abhaya Asthana

Ho S Chen

Richard G Vadimsky

Byung J Han

Maureen Y Lau

Jingsong Zhao

Bernard J Roman

Louis Nelson Ahlquist

Paul A Sullivan

Edith C Ong

Henry Y Kumagai

Maureen Lau

James C Phillips

Robert T Scruton, Sr

Edith T Ong

Jericho J Jacala

Douglas John Dromgoole

Alan E Ferry

Ross J Thompson

Donald D Bacon

Salvador Duenas

Scott C Knauer, Deceased

Carroll H Knauer, Executor

Douglas E Haggan

Donlad D Bacon

Donald Dingley Bacon

The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

Integrated passive devices

A flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Testing integrated circuits

The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Membrane test method and apparatus for integrated circuit testing

The specification describes integrated circuit air isolated crossover interconnections designed for flip chip multi-chip module interconnection technology. The crossovers are made using a crossover interconnection substrate separate from the interconnection substrate of the integrated circuit. In one embodiment the integrated circuit is flip chip bonded to a multi-chip or multi-component interconnection substrate, and the crossover interconnections are made through solder bumps or balls soldered to a conductive layer on the crossover interconnection substrate. In another embodiment the crossover is made via a crossover substrate flip chip bonded to an integrated circuit mounted on a multi-chip or multi-component interconnection substrate.

Air isolated crossovers

The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.

Method of testing and constructing monolithic multi-chip modules

The specification describes a multi-chip IC package in which IC chips are flip-chip bonded to both sides of a flexible substrate. The upper (or lower) surface of the flexible substrate is bonded to a rigid support substrate with openings in the support substrate to accommodate the IC chips bonded to the upper (or lower) surface of the flexible substrate. In a preferred embodiment a plurality of IC memory chips are mounted on one side of the flexible substrate and one or more logic chips to the other. A very thin flexible substrate is used to optimize the length of through hole interconnections between the memory and logic devices. If logic chips are flip-chip mounted in the cavity formed by the openings, a heat sink plate can be used to both cap the cavity and make effective thermal contact the backside of the logic chips.

High performance multi-chip IC package

The specification describes an IC test apparatus having a test bed with sockets adapted to engage arrays of I/O solder balls/bumps on the IC chip. In one embodiment the sockets are provided with through holes to interconnect the solder bumps to the next board level with minimum electrical path length thereby reducing parasitic capacitive coupling. In another embodiment the sockets in the test bed are formed by intersecting V-grooves. If pairs of intersecting V-grooves are used, pyramid shaped features are produced at the bottom of each socket. Both the sharp edges formed by the intersecting V-grooves and the pyramid provide contact enhancement between the solder bumps and the test bed. The test bed can be made as a universal blank for a given solder bump pitch. The desired test circuit is formed at the next board level.

Methods and apparatus for testing integrated circuits

A multi-chip module (&ldquo;MCM&rdquo;) and methods of operation and manufacture thereof. The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, the first separate IC chip including first and second circuit portions coupled together by at least one signal conductor, and (3) interconnecting means that directly couples at least one signal conductor of the first separate IC chip to the second separate IC chip, the interconnecting means bypassing the second circuit portion of the first separate IC chip.

Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module

The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.

Multi-chip ball grid array IC packages

The specification describes packaging assemblies for micro-electronic machined mechanical systems (MEMS). The MEMS devices in these package assemblies are based on silicon MEMS devices on a silicon support and the MEMS devices and the silicon support are mechanically isolated from foreign materials. Foreign materials pose the potential for differential thermal expansion that deleteriously affects optical alignment in the MEMS devices. In a preferred embodiment the MEMS devices are enclosed in an all-silicon chamber. Mechanical isolation is also aided by using a pin contact array for interconnecting the silicon support substrate for the MEMS devices to the next interconnect level. The use of the pin contact array also allows the MEMS devices to be easily demountable for replacement or repair.

Packaging micromechanical devices

The specification describes interconnection strategies for micro-electronic machined mechanical systems (MEMS). Typical MEMS device array comprise a large number of individual mechanical devices each electrically driven by multi-chip modules (MCMs). High density interconnection is achieved by mounting the MCMs mounted on both sides of a system interconnection substrate. Overall interconnection length is reduced by locating the MCMs in a common circuit driving a given mechanical element on opposite sides of the system interconnection substrate and interconnecting them using vias through the substrate. Rapid replacement/repair is facilitated by mounted all active elements in sockets using contact pin arrays for electrical connections. In service reliability is obtained by providing spare sockets for redundant MCMs.

Interconnecting micromechanical devices

The specification describes interconnection assemblies for silicon-on-silicon multichip modules. The silicon-on-silicon MCMs are mounted on epoxy/glass laminates which have a coefficient of thermal expansion (CTE) that essentially matches the CTE of silicon. In the preferred embodiment the assembly is a PC card with card edge connectors, i.e. without fixed solder interlevel interconnections, so that the CTE of the epoxy laminate comprising the card can be modified without regard to potential mismatch with a mother board.

Packaging silicon on silicon multichip modules

A bandpass planar filter (,) comprises a signal input and a signal output (,), and one or more resonator elements (,) coupled serially end-to-end between the input and the output across gaps (,) that separate the elements from the input, the output, and from each other. The resonator elements form a serpentine shape such that at least two portions of the serpentine shape are positioned side-by-side parallel to each other separated by a spacing (,). The side-by-side portions effect additional coupling between the resonator elements that forms a notch (transmission zero) (,) in the passband (,) of the filter. The input, output, and resonator elements are etched into one surface (,) of a PC board (,); the other surface (,) of the PC board forms a ground plane of the filter, and the substrate (,) of the PC board forms a dielectric of the filter.

Method of tuning a planar filter with additional coupling created by bent resonator elements

A multi-chip module (&ldquo;MCM&rdquo;) and methods of operation and manufacture thereof The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, the first separate IC chip including first and second circuit portions coupled together by at least one signal conductor, and (3) interconnecting means that directly couples at least one signal conductor of the first separate IC chip to the second separate IC chip, the interconnecting means bypassing the second circuit portion of the first separate IC chip.

The specification describes methods for manufacturing thin tiles for IC packages using thinning techniques. The method includes the step of thinning the IC devices in chip form. This is achieved at the final stage of assembly where the chips are flip-chip bonded to the substrate and the backside of the chips is exposed for thinning. Using this approach, final chip thickness of the order of 2-8 mils can be produced and overall package thickness is dramatically reduced.

Low profile integrated circuit packages

Growing community of inventors

Berkeley Heights, NJ, United States of America

King Lien Tai