Taiwan Semiconductor Manufacturing Comp. Ltd.

Hewlett-packard Company

Agilent Technologies, Inc.

Other

Kim Hong Chen

Shin-Puu Jeng

Wensen Hung

Szu-Po Huang

Chi-Hsi Wu

Hsiang-Fan Lee

Shang-Yun Hou

Chen-Hua Douglas Yu

Hsin-Yu Pan

Jacques Leibovitz

Daniel J Miller

Wei-Cheng Wu

Chao-Wen Shih

Han-Ping Pu

Tsung-Ding Wang

Chien Ling Hwang

Cheng-Chieh Hsieh

Hsien-Pin Hu

Jung Wei Cheng

Clinton Chao

Robert Keith Crawford

Mark Shane Peng

Voddarahalli K Nagesh

Jung Cheng Ko

An-Jhih Su

Lewis R Dove

Tjandra Winata Karta

Tsorng-Dih Yuan

Chao-Shun Hsu

Louis Chaochiuan Liu

Cheng-Cheng Chang

Hsiang-fan Lee

Vaddoarahalli K Nagesh

Bahram Afshari

Lewis Chu

Johnny Monis Nigos

Soojin Choi

Chun Yee Chan

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

3DIC packaging with hot spot thermal management features

An integrated circuit package and a method of fabrication of the same are provided. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.

Package with embedded heat dissipation features

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

3D semiconductor package interposer with die cavity

Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.

Packaged semiconductor devices

Methods of cooling packaged semiconductor devices

An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour lid over the first die stack and second die stack. The contour lid includes a first thermal conductive portion over the first die stack, a second thermal conductive portion over the second die stack, and a thermal barrier portion between the first thermal conductive portion and the second thermal conductive portion. The thermal barrier portion includes a low thermal conductivity material.

Semiconductor packages with thermal management features for reduced thermal crosstalk

A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein.

3DIC package and methods of forming the same

An integrated circuit package and a method of fabrication of the same are introduced. An opening is formed in a substrate. An embedded heat dissipation feature (eHDF) is placed in the opening in the substrate and is attached to the substrate using a high thermal conductivity adhesive. One or more bonded chips are attached to the substrate using a flip-chip method. The eHDF is thermally attached to one or more hot spots of the bonded chips. In some embodiments, the eHDF may comprise multiple physically disconnected portions. In other embodiments, the eHDF may have a perforated structure.

A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending laterally beyond a respective edge of the first die. The package further includes a first Thermal Interface Material (TIM) over and contacting a top surface of the first die, a heat dissipating lid having a first bottom surface contacting the first TIM, a second TIM over and contacting the second portion of the second die, and a heat dissipating ring having a portion over and contacting the second TIM. The heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring has a plurality of fins and a plurality of recesses separating the plurality of fins from each other.

3DIC packages with heat dissipation structures

Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.

Method of forming 3D integrated circuit package with panel type lid

Growing community of inventors

Fremont, CA, United States of America

Kim Hong Chen