Stats Chippac Pte. Ltd.

Ki Youn Jang

Hun Teak Lee

Hyung Jun Jeon

Jong Kook Kim

ChulSik Kim

JoHyun Bae

YoungMin Kim

Il Kwon Shim

HeeJo Chi

NamJu Cho

Sungmin Song

YoungJoon Kim

Taewoo Kang

JaeHyun Lee

Haengcheol Choi

Dae-Wook Yang

DaeSik Choi

Jong-Woo Ha

DeokKyung Yang

In Sang Yoon

KyungHoon Lee

YoungChul Kim

Jong Wook Ju

DongSoo Moon

Oh Han Kim

Seong Won Park

SungEun Park

DokOk Yu

Chul Sik Kim

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Integrated circuit packaging system with connection structure and method of manufacture thereof

In a semiconductor assembly having stacked elements, discrete bumps made of a polymer such as an electrically nonconductive epoxy are interposed between the upper surface of a substrate and the lower surface of the overhanging part of an elevated element (die or package) with the discrete bump directly under bond sites on the elevated element.

Epoxy bump for overhang die

An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess.

Integrated circuit package system employing mold flash prevention technology

An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.

Electronic system with expansion feature

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.

Integrated circuit packaging system with film assistance mold and method of manufacture thereof

A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.

Semiconductor system with fine pitch lead fingers and method of manufacturing thereof

A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.

Integrated circuit packaging system with routable underlayer and method of  manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.

Integrated circuit packaging system with package-on-package and method of manufacture thereof

A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.

Shielded stacked integrated circuit packaging system and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.

Integrated circuit packaging system with stacked lead and method of manufacture thereof

A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.

Semiconductor package system with fine pitch lead fingers and method of manufacturing thereof

An integrated circuit package system that includes: providing a support structure including an integrated circuit and an electrical contact adjacent thereto; providing a first mold having a first cavity with a projection and a recess for collecting flash; engaging the first mold on the support structure with the first cavity over at least a portion of the integrated circuit and the projection and the recess between the at least a portion of the integrated circuit and the electrical contact; and injecting encapsulation material into the first cavity.

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate cavity; mounting a bottom flip chip die below the substrate; mounting an internal integrated circuit die above the substrate; filling between the internal integrated circuit die and the substrate and between the bottom flip chip die and the substrate with a substance filling through the substrate cavity; and encapsulating the internal integrated circuit die with an encapsulation.

Integrated circuit packaging system using bottom flip chip die bonding and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.

Growing community of inventors

Ichon-si, South Korea

Ki Youn Jang