Samsung Electronics Co., Ltd.

Ki-hyun Park

Sang-Hoon Shin

Pyung-moon Zhang

Yong-Sik Park

Seung-ho Ok

Bo-un Yoon

Dong-Chan Kim

Byoung-ho Kwon

Jong-Su Kim

Choong-seob Shin

A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters including a first test parameter and a second test parameter and perform a test on at least one memory core. The method includes setting a sweep range comprising a sweep start point of the first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

Built-in self-test (BIST) circuit, memory device including the same, and method of operating the BIST circuit

A built-in self-test (BIST) circuit and a method of operating BIST circuit is disclosed. The BIST circuit is configured to generate a test pattern based on a plurality of test parameters and perform a test on at least one memory core. The method includes setting a sweep range including a sweep start point of a first test parameter and a sweep end point thereof; generating a first test pattern corresponding to each sweep point of the sweep range from the sweep start point of the first test parameter and the sweep end point thereof and providing the first test pattern to the at least one memory core; receiving output data corresponding to the first test pattern from the at least one memory core and comparing the output data and a predetermined reference data; and generating first test result information based on results of the comparing.

A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Methods of manufacturing semiconductor devices using alignment marks to align layers

Growing community of inventors

Seoul, South Korea

Ki-hyun Park