Samsung Electronics Co., Ltd.

Kyungpook National University Industry-academic Cooperation Foundation

Ki-ha Hong

Jai-kwang Shin

Jong-seob Kim

Jae-joon Oh

Hyuk-Soon Choi

In-jun Hwang

Sung-hoon Lee

Young-Gu Jin

Jong-bong Ha

Young-Jin Cho

Ho-jung Kim

Sang-moon Lee

Kyoung-yeon Kim

Eui-chul Hwang

Jae-woong Hyun

Sung-il Park

Hyuk-soon Choi

Yoon-Dong Park

Chang-jung Kim

In-kyeong Yoo

Jongseob Kim

Sungil Park

Young-gu Jin

Chang-yong Um

Jae-kwang Shin

Sun-ae Seo

Suk-Pil Kim

Myoung-jae Lee

Hyun-jong Chung

U-in Chung

Dong-hun Kang

Kwang-Hee Kim

Dong-seok Kim

Jung-hee Lee

Ki-won Kim

Noe-jung Park

Jai Kwang Shin

Ki-sik Im

Kyoung-won Park

In-jun Whang

Jeong-seob Kim

A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.

High electron mobility transistors and methods of fabricating the same

A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Method of manufacturing a semiconductor device including a gate electrode on a protruding group III-V material layer

High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer.

High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same

Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer.

Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices

High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer.

High electron mobility transistors including lightly doped drain regions and methods of manufacturing the same

Semiconductor device including a gate electrode on a protruding group III-V material layer and method of manufacturing the semiconductor device

Semiconductor device including a gate electrode on a protruding group III-V material layer

The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Methods of manufacturing high electron mobility transistors

High electron mobility transistors (HEMTs) including a cavity below a drain and methods of manufacturing HEMTS including removing a portion of a substrate below a drain.

High electron mobility transistors and methods of manufacturing the same

According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer and a channel layer. The channel layer may include an effective channel region and a high resistivity region. The effective channel region may be between the high resistivity region and the channel supply layer. The high resistivity region may be a region into which impurities are ion-implanted. According to example embodiments, a method of forming a HEMT includes forming a device unit, including a channel layer and a channel supply layer, on a first substrate; adhering a second substrate to the device unit; removing the first substrate; and forming a high resistivity region by ion-implanting impurities into at least a portion of the channel layer.

According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device

According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.

Power electronic device and method of manufacturing the same

Growing community of inventors

Cheonan-si, South Korea

Ki-ha Hong