Intel Corporation

Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Kevin X Zhang

Zhanping Chen

Fatih Hamzaoglu

Dinesh Somasekhar

Liqiong Wei

Sarvesh H Kulkarni

Vivek K De

Yibin Ye

Thomas D Fletcher

Yih Wang

Zhiyong Ma

Bo Zheng

Xianghong Tong

Kevin D Johnson

Walid M Hafez

Muhammad M Khellah

Swaminathan Sivakumar

Nick Lindert

Krishnan Ravichandran

Nam Sung Kim

Gunjan H Pandya

Swaroop Ghosh

Micah Barany

Matthew B Pedersen

Bob Jackson

Brian S Doyle

Samuel D Naffziger

Stefan Rusu

Wei P Chen

Don J Nguyen

Christopher J Jezewski

Ali Keshavarzi

Gregory F Taylor

John J Wuu

Balaji Srinivasan

Mandar S Joshi

Jonathan P Douglas

Jun He

Donald R Weiss

Praveen Mosalikanti

Eric A Karl

Uddalak Bhattacharya

Pramod Kolar

M Clair Webb

Daniel J Lenehan

Tsung-yung Jonathan Chang

Lin Ma

Yong-Gee Ng

Hyunwoo Nho

Mesut Meterelliyoz

Jonathan Shoemaker

Ming Chieh Huang

Stephen Wu

Faith Hamzaoglu

Siufu Chiu

Meterelliyoz Mesut

Tsung-Yung Chang

Yih (Eric) Wang

Ligiong Wei

Jenny R C Johnson

Jenny R Carman

Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Methods of forming secured metal gate antifuse structures

Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.

DRAM with pulse sense amp

Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

Bitline floating during non-access mode for memory arrays

A 6FDRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.

6F2 DRAM cell

Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

Adaptive and dynamic stability enhancement for memories

A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.

Programmable read only memory

A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

Hierarchical DRAM sensing

Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Antifuse programmable memory array

A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.

Tamper resistant fuse design

A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

Common plate capacitor array connections, and processes of making same

A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.

Area efficient programmable read only memory (PROM) array

In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

Cache leakage shut-off mechanism

A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

Fuse cell array with redundancy features

An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin. A fuse cell may include first and second fuse cells, and first and second resistance devices. The first resistance device may be configured to adjust a first voltage output from the first fuse cell, and the second resistance device may be configured to adjust a second voltage output from the second fuse cell. The first and second resistance devices may be configured adjust the first and second voltages asymmetrically.

Fuse cell having adjustable sensing margin

Growing community of inventors

Portland, OR, United States of America

Kevin X Zhang