International Business Machines Corporation

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Globalfoundries Inc.

Semiconductor Components Industries, LLC

Infineon Technologies Ag

Advanced Micro Devices Corporation

Kevin McStay

Geng Wang

Chengwen Pei

Jeffrey Bowman Johnson

Yanli Zhang

Paul Christian Parries

Dureseti Chidambarrao

Jeffrey P Gambino

Jack Allan Mandelman

Shreesh Narasimha

Brian Joseph Greene

Joseph Ervin

Marc Allen Sulfridge

David Michael Fried

Richard A Mauritzson

David T Price

Gan Wang

Michael Gerard Keyes

Ryan Rettmann

Kangguo Cheng

William R Tonti

Ramachandra Divakaruni

Kevin K Chan

Judson Robert Holt

Michael Patrick Chudzik

Pranita Kulkarni

Anthony I Chou

Dae-Gyu Park

Russell J Houghton

Gregory Gower Freeman

Mark B Ketchen

Werner A Rausch

Thomas M Maffitt

Edward P Maciejewski

Thomas Safron Kanarsky

Oliver Desmond Patterson

Rajesh Rengarajan

Yujun Li

Mark David Jacunski

Mary Elizabeth Weybright

Frank Bin Yang

Ishtiaq Ahsan

Kil-Ho Lee

Johan W Weijtmans

Jophy Stephen Koshy

Yujun c/o Ibm United Kingdom Ltd Li

An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

Semiconductor devices with single-photon avalanche diodes and isolation structures

Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.

Structure and method to control bottom corner threshold in an SOI device

A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

Merged source drain epitaxy

A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

FET structures with trench implantation to improve back channel leakage and body resistance

A semiconductor device structure having an isolation region and method of manufacturing the same are provided. The semiconductor device structure includes a silicon-on-insulator (SOI) substrate. A plurality of gates is formed on the SOI substrate. The semiconductor device structure further includes trenches having sidewalls, formed between each of the plurality of gates. The semiconductor device structure further includes an epitaxial lateral growth layer formed in the trenches. The epitaxial lateral growth layer is grown laterally from the opposing sidewalls of the trenches, so that the epitaxial lateral growth layer encloses a portion of the trenches extended into the SOI substrate. The epitaxial lateral growth layer is formed in such way that it includes an air gap region overlying a buried dielectric layer of the SOI substrate.

Isolation in CMOSFET devices utilizing buried air bags

An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.

Gated diode structure and method including relaxed liner

A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

Transistor having V-shaped embedded stressor

A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection.

Test structure for resistive open detection using voltage contrast inspection and related methods

A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle &#x3b8;+&#x3b4; with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle &#x3b8; with respect to vertical of a dopant into the channel below the source.

Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling

Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants&mdash;an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

Vertical MOSFET with horizontally graded channel doping

An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage (&ldquo;V &rdquo;) monitor, a wordline on voltage (&ldquo;V &rdquo;) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (&ldquo;V &rdquo;) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

Wordline on and off voltage compensation circuit based on the array device threshold voltage

Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

Vertical MOSFET with asymmetrically graded channel doping

In generating first and second voltages (VPP and WLL) for respectively activating and deactivating transistors of a DRAM array that transfer charge to cells of the DRAM array, the second voltage can be lowered to compensate for a threshold voltage (Vt) that is lower than a nominal threshold voltage value (Vt ). Furthermore, the first voltage is tracked together with the second voltage in order to maintain a generally constant voltage swing (V ) therebetween.

Combined tracking of WLL and VPP low threshold voltage in DRAM array

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Hopewell Junction, NY, United States of America

Kevin McStay