General Electric Company

Lockheed Martin Corporation

Other

United States of America As Represented by the Secretary of the Air Force

Martin Marietta Corporation

Kevin Matthew Durocher

Richard J Saia

Paul Alan McConnelee

James Wilson Rose

Christopher James Kapusta

Raymond Albert Fillion

Donald Paul Cunningham

Ernest Wayne Balch

Scott Sheridan Smith

Herbert S Cole

Bernard Gorowitz

Vikram Bidare Krishnamurthy

Arun Virupaksha Gowda

Thomas Bert Gorczyca

Richard Alfred Beaupre

Charles Gerard Woychik

Joseph Alfred Iannotti

William Edward Burdick, Jr

Mario Ghezzo

Leonard Richard Douglas

Ronald Frank Kolc

Bharat S Bagepalli

Stanton Earl Weaver, Jr

Stephen Daley Arthur

Robert Gideon Wodnicki

Charles Edward Baumgartner

Eladio Clemente Delgado

Renato Guida

Matthew Christian Nielsen

David Martin Mills

David Richard Esler

Jeffrey Jon Shaw

Paul Jeffrey Gillespie

Elizabeth Ann Burke

Laura A Principe

Robert J Wojnarowski

Bin Wei

Mehmet Arik

John Eric Tkaczyk

Lowell Scott Smith

Hendrik Pieter Jacobus De Bock

Kenneth Scott Kump

Daniel David Harrison

Hua Xia

Glen Peter Koste

William Hullinger Huber

Abdelaziz Ikhlef

David Mulford Shaddock

George Theodore Dalakos

Robert Stephen Lewandowski

Wei-Cheng Tian

James Enrico Sabatini

Stacey Joy Kennerly

Henri Souchay

Haochuan Jiang

Dalong Zhong

Axel Busboom

George Charles Sogoian

Mark S Maggio

Boon Kwee Lee

Oliver Richard Astley

Donna Marie Sherman

David A Chartrand

William Gregg Hawkins

Vladimir Anatolievich Lobastov

Christopher Michael Eastman

Stacey Joy Goodwin

Piet Moeleker

Donald Cunningham

David Joseph Andrews

Min Yuan

Yuru Alexeyevich Plotnikov

David DeCrescente, Jr

Deng Tao

Richard Joseph Saia

Paul Alan Mcconnelee

Scott Smith

Various methods and systems are provided for forming a flexible circuit. In one example, a method includes forming a flexible circuit comprising a plurality of contact pads arranged into a plurality of rows, each contact pad of a given row electrically coupled to one another via electrical traces and each contact pad including a via, electroplating the flexible circuit, including electroplating each via, with at least a first material, and upon confirming connectivity of each via, cutting at least some of the electrical traces at least partially.

Methods and systems for a flexible circuit

An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. A method of manufacturing an electrical interconnect assembly includes forming at least one top side contact pad on a top surface of a mounting substrate and depositing a metallization layer on the top side contact pad(s), on an exposed portion of the top surface, and into via(s) formed through a thickness of the mounting substrate.

Electrical interconnect for an integrated circuit package and method of making same

An electrical interconnect assembly includes an insulating substrate, upper conductive pads coupled to a top surface of the insulating substrate, and lower conductive pads coupled to a bottom surface of the insulating substrate. The upper conductive pads and the lower conductive pads comprise an electrically conductive material. A metallization layer is deposited on the top surface of the insulating substrate and the upper conductive pads. The metallization layer extends through vias formed through a thickness of the insulating substrate to contact a top surface of the lower conductive pads.

A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.

An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

An interconnect device and a method for fabricating same. An embodiment of the invention includes sequential steps of providing a flexible substrate, forming vias through the flexible substrate, applying a conductive seed layer including first and second portions, applying conductive materials including first and second portions, copper plating the substrate, and then removing the second portions of the conductive seed layer and the conductive materials.

Method of fabricating an interconnect device

A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board.

Circuit board including mask for controlling flow of solder

A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

System of chip package build-up

Detector modules for an imaging system and methods of manufacturing are provided. One detector module includes a substrate, a direct conversion sensor material coupled to the substrate and a flexible interconnect electrically coupled to the direct conversion sensor material and configured to provide readout of electrical signals generated by the direct conversion sensor material. The detector module also includes at least one illumination source for illuminating the direct conversion sensor material.

Detector modules for imaging systems and methods of manufacturing

A method of protecting sensitive components prior to, during or subsequent to advanced die packaging processing includes applying a metal stack layer such as titanium/copper (Ti/Cu) onto the front surface of a die assembly such that the die assembly front surface is covered with the metal stack layer. A layer of titanium/copper/titanium (Ti/Cu/Ti) or a solder alloy is also applied to the back surface of the die assembly such that the back surface of the die assembly is covered with the Ti/Cu/Ti layer or solder alloy. The front surface metal stack layer and the back surface Ti/Cu/Ti layer or solder alloy prevent degradation of die metallization prior to, during or subsequent to the advanced die packaging processing.

Component protection for advanced packaging applications

An ultrasound acoustic assembly includes a number of ultrasound acoustic arrays, each array comprising an acoustic stack comprising a piezoelectric layer assembled with at least one acoustic impedance dematching layer and with a support layer. The acoustic stack defines a number of dicing kerfs and a number of acoustic elements, such that the dicing kerfs are formed between neighboring ones of the acoustic elements. The dicing kerfs extend through the piezoelectric layer and through the acoustic impedance dematching layer(s) but extend only partially through the support layer. The ultrasound acoustic assembly further includes a number of application specific integrated circuit (ASIC) die. Each ultrasound acoustic array is coupled to a respective ASIC die to form a respective acoustic-electric transducer module. Methods of manufacture are also provided.

Ultrasound acoustic assemblies and methods of manufacture

Method of chip package build-up

An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.

Interconnect structure

An interface circuit for a sensor array is provided. The interface circuit may be made up of an integrated circuit package that provides a first region and a second region. The first region may be spaced apart and opposite to the second region of the package. The first region of the package may provide a plurality of interfaces for interconnecting to an integrated circuit in the package a plurality of signals from the sensor array and having a first electrical characteristic, such as analog and test signals. The second region of the package may provide a plurality of interfaces for interconnecting to the integrated circuit a plurality of signals having at least one electrical characteristic different than the first characteristic, such as power and operational digital signals.

Electrical interface for a sensor array

Growing community of inventors

Waterford, NY, United States of America

Kevin Matthew Durocher