Intel Corporation

Hewlett-packard Development Company, L.p.

Kevin Liao

Russell C Brockmann

Christopher Allan Poirier

Joel D Lamb

An address space of a random access memory (&ldquo;RAM&rdquo;) is overlaid over an address space of a read-only memory (&ldquo;ROM&rdquo;) minimizing traditional address bits and loading of an address decoder. Word lines in the ROM in the overlap region are constructed without programming FETs. When the overlap region is addressed, the ROM is unable to change a pre-charged level of the ROM because of the lack of programming FETs. The RAM, however, is free to either leave the pre-charged level unchanged or to drive a node, as required. Thus, conflicts between the ROM and the RAM in the overlap region are eliminated and additional address bit are saved, and loading of address decoders is minimized.

Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM

A method and apparatus are provided for sensing and temporarily latching data signals from memory cells. According to one embodiment, data signals are sensed from memory cells and temporarily latched on an output signal. During a first phase of a clock cycle, multiple input bit-lines are precharged. Subsequently, a discharged input bit-line is sensed during a second phase of the clock cycle. Responsive to the sensing step, the output signal is set to a first state and maintained for at least one clock cycle. According to another embodiment, a multiple input bit-line detecting circuit includes multiple input bit-lines, precharge logic, and output logic. The multiple input bit-lines are configured to be coupled to a bit-line hierarchy of a memory device. The precharge logic is coupled to each of the input bit-lines and is configured to precharge each of the input bit-lines during a first phase of a clock cycle. The output logic is operatively coupled to the multiple input bit-lines to set an output signal to a first state and maintain the first state on the output signal for at least one clock cycle in response to one or more of the input bit-lines being discharged.

Growing community of inventors

Fort Collins, CO, United States of America

Kevin Liao