Freescale Semiconductor,inc.

Huntsman Petrochemical Corporation

Kevin John Hess

Chu-Chung Lee

Michael B McShane

Perry H Pelley

James W Miller

Tu-Anh N Tran

Wheeler C Crawford

Tab Allen Stephens

Trent Uehling

Richard J Clark

Randall Keith Evans

Christopher S Henkee

Gerald W Cummings

Richard J Dominguez

Susan H Downey

Cheng Choi Yong

Edward Outlaw Travis, Jr

Brett P Wilkerson

George R Leal

Scott K Pozder

Robert Joseph Wenzel

Heng Keong Yip

James Patrick Johnston

Kian Leong Chin

Michael A Stockinger

Lan Chu Tan

Peter R Harper

Ruiqi Tian

Pak Leung

Yuan Yuan

Jie-Hua Zhao

David G Wontor

Min Ding

Fuaida Harun

Peng Su

Patrick Johnston

Richard Joseph Gilbert Dominguez

Donna Woosley, Legal Representative

Katie C Yu

Michael V Leoni

An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Integrated circuit package with voltage distributor

Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material. The structure may include a gold free air ball in contact with the diffusion retardant layer.

Localized alloying for improved bond reliability

An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.

Techniques for reducing inductance in through-die vias of an electronic assembly

A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.

Stacked semiconductor devices

A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.

Stacked semiconductor die with continuous conductive vias

A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Packaged integrated circuit using wire bonds

A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.

A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings.

Semiconductor device package

A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Fused buss for plating features on a semiconductor die

A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Molded semiconductor package having a filler material

An integrated circuit includes a high speed circuit, an interconnect pad, a passivation layer under the interconnect pad, a first patterned metal layer, and a first via. The high speed circuit is for a high speed signal at a terminal of the high speed circuit. The interconnect pad is on a top surface of the integrated circuit structure. The first patterned metal layer is under the passivation layer having a first portion and a second portion. The first portion of the first patterned metal layer is connected to the terminal of the high speed circuit. The second portion of the first patterned metal layer is under the interconnect pad and is electrically floating when the high frequency signal is present on the interconnect pad portion. The result is reduced capacitive loading on the high speed signal which improves performance.

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Austin, TX, United States of America

Kevin John Hess