North Carolina State University

Nitronex Corporation

International Rectifier Corporation

Macom Technology Solutions Holdings, Inc.

Infineon Technologies Americas Corp.

Kevin J Linthicum

Thomas Gehrke

Robert F Davis

Edwin Lanier Piner

T Warren Weeks, Jr

Pradeep Rajagopal

Darren B Thomson

John Claassen Roberts

Allen W Hanson

Ricardo M Borges

Jerry Wayne Johnson

James W Cook, Jr

Robert Joseph Therrien

Walter H Nagy

Sameer Singhal

Eric Porter Carlson

Jeffrey D Brown

Apurva D Chaudhari

Andrei Vescan

Tsvetanka Zheleva

Scott A Smith

Kieran M Tracy

Warren Weeks

Semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a substrate, a III-nitride material region over a top surface of the substrate, a first species implanted within at least one region of surface region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate, and a second species implanted within at least one region of the III-nitride material region. The second species can be implanted in a second pattern spatially defined across the lateral dimension of the substrate. The surface region of the substrate includes a parasitic channel. The at least one region of the substrate in which the first species is implanted includes a low-conductivity parasitic channel or is free of the parasitic channel.

Parasitic channel mitigation in semiconductor structures

Semiconductor structures and methods of forming semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a semiconductor substrate and a III-nitride material region over a top surface of the semiconductor substrate. The semiconductor substrate includes a bulk region below the top surface and a parasitic channel that extends to a depth from the top surface toward the bulk region of the semiconductor substrate. The parasitic channel comprises a first region and a second region. The first region of the parasitic channel comprises an implanted species having a relative atomic mass of less than 5, and the second region of the parasitic channel is free from the implanted species or the implanted species is present in the second region at a concentration that is less than in the first region.

Parasitic channel mitigation using silicon carbide diffusion barrier regions

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

A semiconductor material includes a compositionally-graded transition layer, an intermediate later and a gallium nitride material layer. The compositionally-graded transition layer has a back surface and a top surface, and includes a gallium nitride alloy. The gallium concentration in the compositionally-graded transition layer increases from the back surface to the front surface. The intermediate layer is formed under the compositionally-graded transition layer. The gallium nitride material layer is formed over the compositionally-graded transition layer, and has a crack level of less than 0.005 &#x3bc;m/&#x3bc;m.

Semiconductor material having a compositionally-graded transition layer

Parasitic channel mitigation using elemental diboride diffusion barrier regions

III-nitride semiconductor structures comprising spatially patterned implanted species

Parasitic channel mitigation using rare-earth oxide and/or rare-earth nitride diffusion barrier regions

Parasitic channel mitigation in III-nitride material semiconductor structures

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Semiconductor structure with compositionally-graded transition layer

Gallium nitride devices with discontinuously graded transition layer

III-nitride based semiconductor structure

Gallium nitride semiconductor structures with compositionally-graded transition layer

Gallium nitride devices with aluminum nitride intermediate layer

Gallium nitride devices with aluminum nitride alloy intermediate layer

Gallium nitride devices with gallium nitride alloy intermediate layer

Growing community of inventors

Angier, NC, United States of America

Kevin J Linthicum