Lsi Logic Corporation

Lsi Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

Kevin J Gearhardt

Douglas J Feist

Doug Feist

Anita Greeb

Richard Thomas Schultz

Scott C Savage

Anita Marguerite Ekren

Jonathan P Kuppinger

Michael S Pesce

Darrell L Pruehsner

A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to the device-under-test (DUT) that is configured to receive two reference clock signals from automated test equipment (ATE), i.e. conventional ATE which does not provide test frequencies beyond 200 Mhz, and create two high-speed clock pulses that serve as the launch and capture clocks for the TDF test sequence on the DUT.

High-speed TDF testing on low cost testers using on-chip pulse generators and dual ATE references for rapidchip and ASIC devices

A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.

Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices

An external scan test module that is adapted to act as an interface between an automated tester and a device under test. The external scan test module includes a scan pattern memory to hold scan patterns for at least one configuration of the device under test. A failure log memory holds failure information for the device under test. A controller sends scan input data to the device under test, receives scan output data from the device under test, and sends and receives signals from the automated tester. An interface receives scan patterns.

Scan test expansion module

An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first input that receives a first signal from the tester. A second input receives a second signal from the tester, offset by substantially ninety degrees from the phase of the first signal. A speed select input receives a signal, where the signal is selectively set at one of a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first signal, selectively receives the second signal, and receives the speed select signal, and produces the clock signal. The clock signal is a multiple of the tester frequency that is dependent at least in part upon the setting of the speed select signal and the tester frequency. An input receives the clock signal from the hard macro and provides the clock signal to the integrated circuit during testing.

Testing with high speed pulse generator

Methods and structure for improved high-speed TDF testing using an on-chip PLL and associated logic to generate high speed launch and capture pulses. A reference clock may be applied to a PLL circuit within the integrated circuit under test to generate a higher frequency PLL Clock. Gating Logic features and aspects within the integrated circuit may apply the PLL Clock signal to a TDF Clock signal when so directed by a TDF Enable signal from an external test system. The PLL Clock is applied to the TDF Clock signal path for precisely two clock pulses for use as a launch and capture pulse sequence for TDF testing at higher speeds than the external automated test system may achieve.

Methods and structure for improved high-speed TDF testing using on-chip PLL

A four point measurement technique for testing programmable impedance drivers such as the BZIO buffers contained in RapidChip&#xae; and ASIC devices. Specifically, two test pads are added for taking voltage measurements at additional points. By taking the additional voltage measurements and performing some calculation using Ohm's law, the error components of the testing process are effectively eliminated. The technique is suitable for use at wafer sort where additional device pads can be made available for contact with the automated test equipment (ATE) used in the manufacturing test environment.

Four point measurement technique for programmable impedance drivers RapidChip and ASIC devices

A measurement technique which allows the error components of the testing process to be eliminated by performing a differential-style measurement of the programmable termination resistor network. Since for any given DUT pin which is to be tested, there are multiple possible resistances to be measured, the test process provides that two or more resistance measurements are taken on the same pin. Once those values containing the error components are obtained, they are compared to generate a differential resistance measurement which contains only the actual on-chip DUT resistance with the error components completely removed. The differential value can then be tested against previously defined test limits that are set to guarantee the conformance of the on-chip resistance to the processing specifications. The technique can be applied at either the wafer sort or package test phase of device testing, with the different error components associated with either phase being eliminated.

Technique for measurement of programmable termination resistor networks on rapidchip and ASIC devices

A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.

Analog to digital converter built in self test

A circuit which includes the addition of test points and analog circuitry required to perform a four-point measurement technique. Test points are fed to an analog multiplexer which is under control of test logic added to the design to facilitate the testing. The output of the analog multiplexer is fed directly to an n-bit Analog-to-Digital Converter (ADC), when the number of bits is determined by the measurement resolution required for the circuit to be tested. The ADC is controlled by digital test logic instantiated in the design to perform the BIST operation. A known current is injected and held constant during the entire BIST operation, and the BIST logic performs voltage measurements. The voltage differential is compared by the BIST circuitry based on the values obtained from the ADC. Then, a pass/fail bit can be passed to a signal pin on the device to be compared by the ATE.

Built-in self test technique for programmable impedance drivers for RapidChip and ASIC drivers

A metastability risk simulation analysis device and method for identifying metastability risks of a design. The metastability risk simulation analysis device includes computer readable code which is configured to analyze simulation information relating to the design and determine whether the design presents a metastability risk. Desirably, the computer readable code is configured to determine whether two signals, such as a data signal and a clock signal of a synchronous element of the design, cross over each other thereby presenting a metastability risk, and is configured to generate a summary report identifying those synchronous elements of the design which present a metastability risk. Preferably, the computer readable code is configured to analyze simulation information relating to best case and worst case simulations of the design, and is configured to scan the simulation information to identify an edge of a clock signal and an edge of a data signal of the best case and worst case simulations and determine whether the signals cross each other.

Metastability risk simulation analysis tool and method

A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.

Integrated circuit design using a frequency synthesizer that automatically ensures testability

A scan-based logic test apparatus is provided for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices. The test apparatus is embodied in a test card which is pluggable into a bus slot within a computer. The computer includes a permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data. The test card includes an I/O interface control which interfaces the test card to the computer to permit retrieval of the scan-based pattern data from the permanent memory and which interfaces the test card to the digital tester to permit the tester to supply control signals to the test card. The test card further includes an SRAM memory which is coupled to the I/O interface control. The SRAM memory stores the scan-based pattern data including serial input pattern data and expected serial output pattern data upon retrieval thereof from the permanent memory by the I/O interface control. The test card also includes an IC device interface for coupling the IC device to the SRAM memory and the I/O interface control, such that the serial input pattern data is provided to the IC device and an responsive serial output pattern data is collected from the IC device. The responsive serial output pattern data is compared with the expected serial output pattern data to make a pass/fail decision with respect to the particular IC device under test.

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Fort Collins, CO, United States of America

Kevin J Gearhardt