Motorola Corporation

Freescale Semiconductor,inc.

Synopsys, Inc.

Kevin D Lucas

Michael E Kling

Alfred J Reich

Olubunmi O Adetutu

Bernard J Roman

Stanley Michael Filipiak

Christopher C Hobbs

Yeong-Jyh Tom Lii

Warren D Grobman

William Louis Wilkinson

Yolanda S Musgrove

Avgerinos V Gelatos

Ulrich Karl Klostermann

Rabiul Islam

Chi-Min Yuan

Ajay Jain

Chong-Cheng Fu

Ramnath Venkatraman

Paul G Tsui

Jonathan L Cobb

Kirk J Strozewski

Yudhishthir Prasad Kandel

Cesar M Garza

Zachary Adam Levinson

Hak-Lay Chuang

Ulrich Welling

Clyde H Browning

James Morrow

James N Conner

Marc J Olivares

Yonchan Ban

Yeong Jyh Lii

Wayne D Clark

Christopher D Pettinato

In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Stochastic-aware lithographic models for mask synthesis

Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.

Method and apparatus for determining mask layouts for a spacer-is-dielectric self-aligned double-patterning process

Photoresist on a wafer is exposed using tiles on a mask that improve flare performance. Features that are not to be exposed on the photoresist correspond to features on the mask. The various features are surrounded by other features that vary and thus affect flare differently. Selected features have tiles added nearby but also far enough away to improve uniformity in the effects of flare on the various features that are intended to be present in the photoresist. The tiles are made either very small in width or partially absorbing so that the tiles are not resolved in the photoresist. Thus the tiles reduce flare but do not alter the desired pattern in the photoresist.

Non-resolving mask tiling method for flare reduction

A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.

Semiconductor device and method of forming the same

A method ( ) for correcting lithography error includes generating ( ) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize ( ) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern ( ) has isolated features ( ) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern ( ) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

Lithography correction method and device

A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (,) over a substrate (,). The MOS metallic gate electrode layer (,) is covered with an ARC layer (,). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (,and,) are then selectively masked photoresist (,) that is selectively exposed to deep ultraviolet (DUV) radiation (,). The ARC layer (,) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer

A hardmask layer (,) is formed over insulating layers (,and,), and an antireflective layer (,) is formed overlying the hardmask layer (,). A resist layer (,) is formed overlying the antireflective layer (,), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (,). The exposed surface portion of the antireflective layer (,) and portions of the hardmask layer (,) are etched to expose a surface portion of the insulating layers (,and,), and a feature opening (,) is formed in the insulating layers (,and,). A conductive material (,) is deposited to fill the feature opening (,), and portions of the conductive material (,) lying outside the opening are removed.

Process for forming a combination hardmask and antireflective layer

In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (,) on a semiconductor substrate (,). The dielectric layer (,) is then patterned to form interconnect openings (,). A layer of copper (,) is then formed within the interconnect openings (,). A portion of the copper layer (,) is then removed to form copper interconnects (,) within the interconnect openings (,). A copper barrier layer (,) is then formed overlying the copper interconnects (,). Adhesion between the copper barrier layer (,) and the copper interconnects (,) is improved by exposing the exposed surface of the copper interconnects (,) to a plasma generated using only ammonia as a source gas.

Copper interconnect structure and method of formation

A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.

Tantalum oxide anti-reflective coating (ARC) integrated with a metallic

Lithographic Proximity Correction (LPC) shapes are added (503) to a layer of a layout database file (501). Geometric criteria such as feature width are then used to filter the added LPC shapes (502). The LPC shapes are then modified (505) by determining which LPC shapes are within a predetermined distance from a shape in a layer of the second data base (504). The database file, including the modified LPC shapes, is then used to manufacture a set of lithographic masks (506). The lithographic masks are then used to pattern a set of wafers in the manufacture of integrated circuits (507).

Lithographic proximity correction through subset feature modification

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit design. When this is not the case, exposure energy such as light behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion, and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the circuit designs themselves can be altered so that the final printed results better matches the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Square (142), cross (162), octagon (172), and hammerhead (202) serifs are added to integrated circuit designs by shape manipulation functions to perform two dimensional (2-D) LPC.

Two dimensional lithographic proximity correction using DRC shape

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the elements within the circuit design. When this is not the case, the exposure radiation behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the designs themselves can be altered so that the final printed results better match the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Edge assist shapes and edge biasing features are added to integrated circuit designs by shape manipulation functions to perform one dimensional (1-D) LPC.

One dimensional lithographic proximity correction using DRC shape

A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.

Process for producing and inspecting a lithographic reticle and

A process for designing and forming a reticle (40) as well as the manufacture of a semiconductor substrate (50) using that reticle (40). The present invention places outriggers (32, 34, 36) between features (30) in both dense and semi-dense feature patterns to assist in the patterning of device features. The width of the outriggers can be changed based on pitch and location between features in a semi-dense or dense feature pattern. In one embodiment, the outriggers can be manually or automatically inserted into the layout file after the locations of the attenuating features have been determined. The outriggers are not patterned on the substrate, but assist in forming resist features of uniform width.

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Austin, TX, United States of America

Kevin D Lucas