National Semiconductor Corporation

Lsi Logic Corporation

Other

Kevin C Weaver

Zachary Joshua Gemmill

Henry Acedo

Gengying Gao

Steven Jacobson

William Ng

Terry Barrette

Lakshmi Durbha

Hiep V Nguyen

Visvamohan Yegnashankaran

Emery O Sugasawara

Hengyang James Lin

Hengyang (James) Lin

Chetan Paydenkar

David Zakharian

Smith J Johnson

Geng Ying Gao

Duc Huu Nguyen

Steve E Scott

Jay Hidy

Zhaomin Ji

Usharani Bhimavarapu

Mohan Yegnashankaran

The time required to perform a passive voltage contrast test of an area of interest of a layer of interest is substantially reduced by digitizing a passive voltage contrast image to form contrast data that represents the image, and comparing the contrast data to computer aided design (CAD) data that defines the semiconductor device.

Method of reducing the time required to perform a passive voltage contrast test

In an IC structure and method for debugging or adjusting the parameters of an IC circuitry, edit structures are formed in the IC device and are connected to desired portions of the IC circuitry buy forming vias through the passivation layer overlying the top metal layer and forming metal interconnects.

Built-in design edit structures

Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite ends of the piece of silicon using a FIB system. For capacitance, a dielectric is formed on the piece of silicon, and a layer of metal is formed on the dielectric. Vias are formed to regions on the metal traces, to the piece of silicon, and to the layer of metal using the FIB system.

Method of editing a semiconductor die

A method to de-packaging a semiconductor device to access and test the die within the package. The method involves initially removing molding compound from a first surface of the package to expose the underlying die attach pad of the package. A mask is then formed over the die attach-pad. An etching solution is subsequently introduced through an opening in the mask to etch away the die attach pad. Once the etching is complete, the die attach film is removed. An ohmic contact is then formed on the exposed back surface of the die. The ohmic contact is used to ground the die so that the electrical circuitry on the device will operate properly. Once grounded, the circuitry on the die can be electrically tested and debugged.

De-packaging process for small outline transistor packages

In a stacked die integrated circuit structure, the structure can subsequently be tested by removing any packaging material and separating the die from a die paddle and from each other. The separation can involve the use of chemicals or heat, with or without the use of mechanical force. One aspect of the invention includes making use of specifically chosen adhesives to secure the die to the die paddle and to each other, so that any subsequent removal can readily be achieved.

Process for forming and analyzing stacked die

Disclosed is a method for non-destructive removal of cured epoxy from a wafer backside. A wafer back-coated with epoxy is soaked in an acetone bath for a period of time, allowing degradation of the epoxy coating adhesion strength. The epoxy coating is then peeled or scraped away, leaving the wafer backside ready for a rework or for a reapplication of a new epoxy coating.

Method for non-destructive removal of cured epoxy from wafer backside

Semiconductor die with an editing structure

Point-by-point image contrast values are generated from secondary electron collection during unbiased electron or ion beam bombardment of an integrated circuit (IC) in a vacuum environment to quantify the physical and electrical integrity of connections within the device. These values are stored for each type of circuit cell under standard conditions to quantify and check the performance of individual cells on the device.

E-beam voltage potential circuit performance library

The thickness of a semiconductor wafer is non-destructively measured using infrared (IR) microscopy. The wafer is placed on a stage. A distance between the stage and a detector is then varied so that a first image of the wafer is focused on the detector. When focused, a first separation distance is measured. The distance between the stage and the detector is again varied so that a second image is focused on the detector. When again focused, a second separation distance is measured. The difference between the first and second separation distances is then determined and multiplied by the refractive index of light in silicon.

Non-destructive method of measuring the thickness of a semiconductor wafer

A method and system for detecting the location of a defect within an integrated circuit (IC). With power applied to the IC via its power supply terminals (VDD, VSS), an infrared (IR) laser light is scanned along the X and Y dimensions of a surface of the IC. Reflected IR light and the IC power supply current are measured and processed using Fourier Transformation computations. Based upon the results of such computations, the Z coordinate is determined that corresponds to the depth of the defect within the IC.

System and method for detecting location of a defective electrical connection within an integrated circuit

A method for non-destructively testing an IC device to determine the ESD performance. A laser beam is used to probe the diffusions of the device. The amount of light absorbed by the diffusions is determined by monitoring the degree to which light is reflected by the device. The amount of reflection is related to the ESD susceptibility of the device in that the greater the amount of reflection, the worse the ESD performance of the device.

Method of testing the electrostatic discharge performance of an IC device

An integrated circuit backside preparation process back-thins a die using a dry etch process. A wet etch process decaps the integrated circuit to expose the die. After polishing, the prepared integrated circuit is ready for a backside debug analysis.

Backside IC device preparation process

A vibration resistant test module for use with semiconductor device test apparatus that includes a test module top plate, a test module bottom plate and a plurality of spring-and-wire assemblies. The test module top and bottom plates each have a plurality of openings extending between their upper and lower surfaces. Each of the spring-and-wire assemblies includes an electrically conducting wire with a top wire end and a bottom wire end, a top electrically conducting spring connector attached to the top wire end, and a bottom electrically conducting spring connector attached to the bottom wire end. The spring-and-wire assemblies are threaded through separate openings in the test module top and bottom plates such that the top electrically conducting spring connectors extend above the upper surface of the test module top plate, while the bottom electrically conducting spring connectors extend below the lower surface of the test module bottom plate. The top and bottom electrically conducting spring connectors are used to make secure and vibration resistant electrical connections between the vibration resistant test module and other semiconductor device test apparatus components.

Vibration resistant test module for use with semiconductor device test apparatus

A testing system comprising an electron beam probe, a photon beam probe, and a device under test (DUT) card holder which is positioned between the electron beam probe and the photon beam probe. A first valve is positioned between the electron beam probe and the DUT. A second valve, located on an opposite side of the DUT from the first valve, is positioned between the photon beam probe and the DUT. The first and second valve operate in cooperation to control the pressure surrounding the DUT card. One embodiment of the invention includes a first test chamber and a second test chamber. The first test chamber includes the area between the first side of the DUT card and the first valve. The second test chamber includes the area between the second side of the DUT card and the second valve. The present invention includes a method for using the test system of the present invention to test both the top and bottom surfaces of a semiconductor device. The method for using the test system manipulates the first valve and the second valve to selectively contain a vacuum pressure throughout the first test chamber and the area surrounding the DUT. The present invention includes a method for preparing an integrated circuit (IC) for testing by the testing system of the present invention. The present invention also includes a DUT card which secures and positions the DUT for testing within the testing system.

Electron-electro-optical debug system E2ODS

The present invention advantageously provides a method for obtaining access to an integrated circuit chip encapsulated within a device package. The present method involves positioning a masking material, i.e., gasket, adjacent to the heat spreader of the device package. The gasket includes a cavity which is aligned adjacent a portion of the heat spreader directly above the chip. An etchant injection system is then placed against the gasket. A heat spreader etchant is then injected directly into the cavity such that the etchant contacts the exposed surface of the heat spreader. The etchant is supplied to the cavity until a opening is etched vertically through the thickness of the heat spreader. If the heat spreader is composed of copper plated with nickel, it is preferred that the etchant be a solution of 70% nitric acid heated to about 80.degree. C. Formation of the opening through the heat spreader may expose an adhesive layer. This layer may be removed using abrasion combined with nitric acid solution to expose the underside of the chip.

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San Jose, CA, United States of America

Kevin C Weaver