Samsung Electronics Co., Ltd.

Seoul National University

Keunwook Shin

Hyeonjin Shin

Changseok Lee

Kyung-Eun Byun

Yeonchoo Cho

Hyunjae Song

Changhyun Kim

Seongjun Park

Seunggeol Nam

Eunkyu Lee

Sangwon Kim

Alum Jung

Yunseong Lee

Jinseong Heo

Sanghyun Jo

Yonghoon Kim

Hyunseok Lim

Kibum Kim

Soyoung Lee

Sanghun Lee

Taejin Choi

Janghee Lee

Jaeho Lee

Sangwook Kim

Minsu Seol

Jeonil Lee

Kyungeun Byun

Junghoo Shin

Sungjoo An

Hyunmi Kim

Seungwon Lee

Sangsoo Lee

Hyun Soo Park

Woojin Lee

Dongwook Lee

Sanghoon Ahn

Kwanghee Lee

Minhyun Lee

Hanjin Lim

Taehwan Moon

Hyangsook Lee

Dohyun Lee

Seongjun Jeong

Jongmyeong Lee

Minseok Yoo

Junyoung Kwon

Jeeeun Yang

Donghyun Im

Moonil Jung

Kaoru Yamamoto

Van Luan Nguyen

Jungsoo Yoon

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μmor higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Nanocrystalline graphene and method of forming nanocrystalline graphene

Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having spbonds to carbons having spbonds in the graphene material is 1 or less.

Interconnect structure and electronic device including the same

A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

Wiring including graphene layer and method of manufacturing the same

Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

Thin film structure and electronic device including two-dimensional material

Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.

Interconnect structure, electronic device including the same, and method of manufacturing interconnect structure

A method of pre-treating a substrate on which graphene will be directly formed may include pre-treating the substrate using a pre-treatment gas including at least a carbon source and hydrogen.

Method of pre-treating substrate and method of directly forming graphene using the same

A method of forming nanocrystalline graphene according to an embodiment may include: arranging a substrate having a pattern in a reaction chamber; injecting a reaction gas into the reaction chamber, where the reaction gas includes a carbon source gas, an inert gas, and a hydrogen gas that are mixed; generating a plasma of the reaction gas in the reaction chamber; and directly growing the nanocrystalline graphene on a surface of the pattern using the plasma of the reaction gas at a process temperature. The pattern may include a first material and the substrate may include a second material different from the first material.

Method of forming nanocrystalline graphene

A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

Semiconductor device and electronic apparatus including the semiconductor device

A film deposition method may include preparing a non-planar substrate including a first surface, a second surface, and an inclined surface between the first surface and the second surface; depositing a film having a thickness deviation on the first surface, the second surface, and the inclined surface; and etching the film deposited on the first surface, the second surface, and the inclined surface. A height of the second surface may be different than a height of the first surface.

Film deposition method and element including film deposited by the film deposition method

A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

Metal-to-semiconductor contact including a 2D crystal material layer

A stacked structure may include a first material layer, a two-dimensional material layer on the first material layer, and a second material layer on the two-dimensional material layer. The two-dimensional material layer may include a plurality of holes that each expose a portion of the first material layer. The second material layer may be coupled to the first material layer through the plurality of holes.

Stacked structure including two-dimensional material and method of fabricating the stacked structure

A graphene structure and a method of forming the graphene structure are provided. The graphene structure includes directly grown graphene that is directly grown on a surface of a substrate and has controlled surface energy.

Graphene structure and method of forming the graphene structure

A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

Method of forming graphene

Growing community of inventors

Yongin-si, South Korea

Keunwook Shin