Intel Corporation

Keshavan K Tiruvallur

James B Crossland

Rajesh S Parthasarathy

Shivnandan D Kaushik

Luke Hood

Robert J Greiner

Dion Rodgers

Darrell D Boggs

Amit A Merchant

Frank Binns

Robert G Blankenship

Andrew F Glew

Tessil Thomas

Sridhar Muthrasanallur

Kenneth C Creta

David I Poisner

Shreekant S Thakkar

Scott Dion Rodgers

David W Grawrock

Haitham H Akkary

Nitin V Sarangdhar

Xiang Chris Zou

Sarathy Jayakumar

David Lawrence Hill

Douglas M Carmean

Michael W Rhodehamel

Bruce Querbach

Raymond Scott Tetrick

Herbert H J Hum

Kris G Konigsfeld

Andreas Kleen

Sham M Datta

Tieyu Zheng

Mark B Trobough

Binata Bhattacharyya

Michael Kinney

Chinna B Prudvi

Jayakrishna Guddeti

Hermann Gartler

Vui Yong Liew

David B Sheffield

Rajesh Kota

Rachel Hsu

Madhavan Parthasarathy

Keshavram N Murty

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Jay Joseph Nejedlo

Mukesh Kataria

Lyle E Cool

James J Grealish

Russell J Wunderlich

Salessawi Ferede Yitbarek

Milind A Karnik

Brian Meyer

Abhijit Davare

Joseph E Batz

Priyadarsan Patra

Muntaquim F Chowdhury

William Penner

Rahima K Mohammed

Ridvan A Sahan

Kapila B Udawatta

Wee Hoo Cheah

Yuen Tat Lee

John L Baudrexl

Arun R Ramadorai

Loren James McConnell

Kip C Killpack

Kyle Markley

Thomas Toll

Christian E Iovin

Travis K Goff

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

James A Brayton

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Shivnanda Kaushik

Ruiyu Ni

Jay Lawlor

Charles Holthaus

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Technique for communicating interrupts in a computer system

Methods and apparatus relating to debugging complex multi-core and/or multi-socket systems are described. In one embodiment, a debug controller detects an event corresponding to a failure in a computing system and transmits data corresponding to the event to one of the other debug controllers in the system. Other embodiments are also disclosed and claimed.

Methods and tools to debug complex multi-core, multi-socket QPI based system

Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.

Address space emulation

Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed.

Techniques for broadcasting messages on a point-to-point interconnect

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system.

Opportunistic transmission of software state information within a link based computing system

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.

Processor selection for an interrupt based on willingness to accept the interrupt and on priority

Architectures and techniques that allow legacy pin functionality to be replaced with a 'virtual wire' that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Virtualization of pin functionality in a point-to-point interface

In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.

Processor selection for an interrupt identifying a processor cluster

In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Creation of logical APIC ID with cluster ID and intra-cluster ID

A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.

Technique for broadcasting messages on a point-to-point interconnect

A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

Method and apparatus for processing an event occurrence within a multithreaded processor

Growing community of inventors

Tigard, OR, United States of America

Keshavan K Tiruvallur